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 | 2013 | |
|---|---|---|
| j27 |      | Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid: MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. IEEE Trans. Industrial Informatics 9(1): 527-545 (2013) |
| c95 | | Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid: A compiler infrastructure for embedded heterogeneous MPSoCs. PMAM 2013: 1-10 |
| 2012 | ||
| c94 | | Luis Gabriel Murillo, Juan Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid: Synchronization for hybrid MPSoC full-system simulation. DAC 2012: 121-126 |
| c93 | | Jerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid: Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. DAC 2012: 1266-1271 |
| c92 | | Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Eusse, Rainer Leupers, Gerd Ascheid: Hybrid simulation for extensible processor cores. DATE 2012: 288-291 |
| c91 | | Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel: Virtual platforms: Breaking new grounds. DATE 2012: 685-690 |
| c90 | | Christoph Schumacher, Jan Weinstock, Rainer Leupers, Gerd Ascheid: Scandal: Systemc analysis for nondeterminism anomalies. FDL 2012: 112-119 |
| c89 | | Anastasia Stulova, Rainer Leupers, Gerd Ascheid: Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs. ICSAMOS 2012: 144-151 |
| c88 | | Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS 2012: 278-285 |
| 2011 | ||
| j26 | | Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A retargetable framework for compiler/architecture co-development. Design Autom. for Emb. Sys. 15(3-4): 311-342 (2011) |
| j25 | | Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers: Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. IJERTCS 2(3): 1-20 (2011) |
| j24 | | Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp, Andreas Hoffmann: Checkpointing SystemC-Based Virtual Platforms. IJERTCS 2(4): 21-37 (2011) |
| j23 | | Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee, Hanno Scharwächter, Rainer Leupers: Fast graph-based instruction selection for multi-output instructions. Softw., Pract. Exper. 41(6): 717-736 (2011) |
| c87 | | Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen: Virtual Manycore platforms: Moving towards 100+ processor cores. DATE 2011: 715-720 |
| c86 | | Jerónimo Castrillón, Weihua Sheng, Rainer Leupers: Trends in embedded software synthesis. ICSAMOS 2011: 347-354 |
| c85 | | Felix Engel, Rainer Leupers, Gerd Ascheid, Max Ferger, Marcel Beemster: Enhanced structural analysis for C code reconstruction from IR code. SCOPES 2011: 21-27 |
| 2010 | ||
| j22 | | David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Automatic Generation of Memory Interfaces for ASIPs. IJERTCS 1(3): 1-23 (2010) |
| j21 | | Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Analytical and Simulation-based Design Space Exploration of Software Defined Radios. International Journal of Parallel Programming 38(3-4): 303-321 (2010) |
| j20 | | Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. on Circuits and Systems 57-II(9): 706-710 (2010) |
| c84 | | Rainer Leupers, Jerónimo Castrillón: MPSoC programming using the MAPS compiler. ASP-DAC 2010: 897-902 |
| c83 | | Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann: parSC: synchronous parallel systemc simulation on multi-core host architectures. CODES+ISSS 2010: 241-246 |
| c82 | | Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE 2010: 753-758 |
| c81 | | Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki: Cool MPSoC programming. DATE 2010: 1488-1493 |
| c80 | | Stefan Schürmans, Elias Weingärtner, Torsten Kempf, Gerd Ascheid, Klaus Wehrle, Rainer Leupers: Towards Network Centric Development of Embedded Systems. ICC 2010: 1-6 |
| c79 | | Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout: 2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI 2010: 494-499 |
| c78 | | |
| 2009 | ||
| j19 | | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated verification approach during ADL-driven processor design. Microelectronics Journal 40(7): 1111-1123 (2009) |
| j18 | | Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A SIMD optimization framework for retargetable compilers. TACO 6(1) (2009) |
| j17 | | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 8(2) (2009) |
| c77 | | Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20 |
| c76 | | Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS 2009: 305-314 |
| c75 | | Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl: Programming MPSoC platforms: Road works ahead! DATE 2009: 1584-1589 |
| c74 | | Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid: Task management in MPSoCs: An ASIP approach. ICCAD 2009: 587-594 |
| c73 | | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS 2009: 204-214 |
| c72 | | David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI 2009: 309-314 |
| c71 | | Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design 2009: 281-286 |
| i2 | | Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding. CoRR abs/0910.3427 (2009) |
| i1 | | David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr: Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptology ePrint Archive 2009: 56 (2009) |
| 2008 | ||
| j16 | | Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr: SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. IJES 3(3): 109-118 (2008) |
| j15 | | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr: Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. IJES 3(3): 150-159 (2008) |
| j14 | | Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Power-efficient Instruction Encoding Optimization for Various Architecture Classes. JCP 3(3): 25-38 (2008) |
| j13 | | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 7(4) (2008) |
| j12 | | Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid: A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008) |
| c70 | | Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Multiprocessor performance estimation using hybrid simulation. DAC 2008: 325-330 |
| c69 | | Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda: MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759 |
| c68 | | Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE 2008: 1334-1339 |
| c67 | | Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh: Retargetable Code Optimization for Predicated Execution. DATE 2008: 1492-1497 |
| c66 | | Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle: System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. DATE 2008 |
| 2007 | ||
| b6 |  | Oliver Schliebusch, Heinrich Meyr, Rainer Leupers: Optimized ASIP synthesis from architecture description language models. Kluwer 2007, isbn 978-1-4020-5685-7, pp. I-XIV, 1-193 |
| j11 | | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embedded Comput. Syst. 6(2) (2007) |
| c65 | | Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A fast and generic hybrid simulation approach using C virtual machine. CASES 2007: 3-12 |
| c64 | | Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: HySim: a fast simulation framework for embedded software development. CODES+ISSS 2007: 75-80 |
| c63 | | Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr: A code-generator generator for multi-output instructions. CODES+ISSS 2007: 131-136 |
| c62 | | Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Design space exploration of partially re-configurable embedded processors. DATE 2007: 319-324 |
| c61 | | Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE 2007: 1349-1354 |
| c60 | | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD 2007: 166-171 |
| c59 | | Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194 |
| 2006 | ||
| b5 | | Tim Kogel, Rainer Leupers, Heinrich Meyr: Integrated system-level modeling of network-on-chip enabled multi-processor platforms. Kluwer 2006, isbn 978-1-4020-4825-8, pp. I-XIV, 1-199 |
| j10 | | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers: Offset assignment using simultaneous variable coalescing. ACM Trans. Embedded Comput. Syst. 5(4): 864-883 (2006) |
| j9 | | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. VLSI Signal Processing 43(2-3): 235-246 (2006) |
| c58 | | Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren: Retargetable code optimization with SIMD instructions. CODES+ISSS 2006: 148-153 |
| c57 | | Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini: SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. CODES+ISSS 2006: 167-172 |
| c56 | | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226 |
| c55 | | Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238 |
| c54 | | Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE 2006: 468-473 |
| c53 | | Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, M. Pandey: A design flow for configurable embedded processors based on optimized instruction set extension synthesis. DATE 2006: 581-586 |
| c52 | | Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605 |
| c51 | | Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE 2006: 919-924 |
| c50 | | Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini: An integrated open framework for heterogeneous MPSoC design space exploration. DATE 2006: 1145-1150 |
| c49 | | Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Memory Access Micro-Profiling for ASIP Design. DELTA 2006: 255-262 |
| c48 | | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118 |
| 2005 | ||
| p1 | | Rainer Leupers, Gerd Ascheid: Digital Signal Processors. Handbook of Networked and Embedded Control Systems 2005: 279-294 |
| c47 | | Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP 2005: 154-160 |
| c46 | | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel: A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 |
| c45 | | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 |
| c44 | | Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Fine-grained application source code profiling for ASIP design. DAC 2005: 329-334 |
| c43 | | Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 |
| c42 | | Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: C Compiler Retargeting Based on Instruction Semantics Models. DATE 2005: 1150-1155 |
| c41 | | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171 |
| 2004 | ||
| j8 | | Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr: A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004) |
| c40 | | Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis, Rainer Leupers: Compiler based exploration of DSP energy savings by SIMD operations. ASP-DAC 2004: 838-841 |
| c39 | | Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr: A novel approach for flexible and consistent ADL-driven ASIP design. DAC 2004: 717-722 |
| c38 | | Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl: RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160 |
| c37 | | Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 |
| c36 | | Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 |
| c35 | | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 |
| c34 | | Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 |
| c33 | | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS 2004: 463-473 |
| c32 | | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46 |
| 2003 | ||
| j7 | | Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr: Instruction Scheduler Generation for Retargetable Compilation. IEEE Design & Test of Computers 20(1): 34-41 (2003) |
| c31 | | Rainer Leupers: Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms. CC 2003: 290-302 |
| c30 | | Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 |
| c29 | | Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr: Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267 |
| c28 | | Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl: Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973 |
| c27 | | Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie: Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES 2003: 167-181 |
| c26 | | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers: Improving Offset Assignment through Simultaneous Variable Coalescing. SCOPES 2003: 285-297 |
| 2002 | ||
| b4 | | Andreas Hoffmann, Heinrich Meyr, Rainer Leupers: Architecture exploration for embedded processors with LISA. Kluwer 2002, isbn 978-1-4020-7338-0, pp. I-VIII, 1-230 |
| j6 | | Rainer Leupers: Compiler Design Issues for Embedded Processors. IEEE Design & Test of Computers 19(4): 51-58 (2002) |
| c25 | | Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann: A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27 |
| c24 | | Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr: Application specific compiler/architecture codesign: a case study. LCTES-SCOPES 2002: 185-193 |
| 2001 | ||
| b3 | | Rainer Leupers, Peter Marwedel: Retargetable compiler technology for embedded systems - tools and applications. Kluwer 2001, isbn 978-0-7923-7578-4, pp. I-XI, 1-175 |
| j5 | | Jens Wagner, Rainer Leupers: C compiler design for a network processor. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1302-1308 (2001) |
| c23 | | Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel: Optimized address assignment for DSPs with SIMD memory accesses. ASP-DAC 2001: 415-420 |
| c22 | | Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis: Low-Energy DSP Code Generation Using a Genetic Algorithm. ICCD 2001: 431-437 |
| c21 | | Jens Wagner, Rainer Leupers: C Compiler Design for an Industrial Network Processor. LCTES/OM 2001: 155-164 |
| 2000 | ||
| b2 | | Rainer Leupers: Code optimization techniques for embedded processors - methods, algorithms, and tools. Kluwer 2000, isbn 978-0-7923-7989-8, pp. I-VIII, 1-216 |
| j4 | | Rainer Leupers, Steven Bashford: Graph-based code selection techniques for embedded processors. ACM Trans. Design Autom. Electr. Syst. 5(4): 794-814 (2000) |
| c20 | | |
| c19 | | Rainer Leupers: Register allocation for common subexpressions in DSP data paths. ASP-DAC 2000: 235-240 |
| c18 | | |
| c17 | | |
| 1999 | ||
| j3 | | Steven Bashford, Rainer Leupers: Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Design Autom. for Emb. Sys. 4(2-3): 119-165 (1999) |
| c16 | | Rainer Leupers, Johann Elste, Birger Landwehr: Generation of Interpretive and Compiled Instruction Set Simulators. ASP-DAC 1999: 339-342 |
| c15 | | Steven Bashford, Rainer Leupers: Constraint Driven Code Selection for Fixed-Point DSPs. DAC 1999: 817-822 |
| c14 | | Rainer Leupers: Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. DATE 1999: 105- |
| c13 | | Rainer Leupers, Peter Marwedel: Function inlining under code size constraints for embedded processors. ICCAD 1999: 253-256 |
| c12 | | Anupam Basu, Rainer Leupers, Peter Marwedel: Array Index Allocation under Register Constraints in DSP Programs. VLSI Design 1999: 330-335 |
| 1998 | ||
| j2 | | Rainer Leupers, Peter Marwedel: Retargetable Code Generation Based on Structural Processor Description. Design Autom. for Emb. Sys. 3(1): 75-108 (1998) |
| c11 | | Rainer Leupers, Anupam Basu, Peter Marwedel: Optimized Array Index Computation in DSP Programs. ASP-DAC 1998: 87-92 |
| c10 | | Anupam Basu, Rainer Leupers, Peter Marwedel: Register-Constrained Address Computation in DSP Programs. DATE 1998: 929-930 |
| c9 | | Rainer Leupers, Fabian David: A Uniform Optimization Technique for Offset Assignment Problems. ISSS 1998: 3-8 |
| c8 | | Rainer Leupers: HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. ISSS 1998: 51- |
| 1997 | ||
| b1 | | Rainer Leupers: Retargetable code generation for digital signal processors. Kluwer 1997, isbn 978-0-7923-9958-2, pp. I-X, 1-210 |
| j1 | | Rainer Leupers, Peter Marwedel: Time-constrained code compaction for DSPs. IEEE Trans. VLSI Syst. 5(1): 112-122 (1997) |
| c7 | | Rainer Leupers, Peter Marwedel: Retargetable generation of code selectors from HDL processor models. ED&TC 1997: 140-144 |
| 1996 | ||
| c6 | | Rainer Leupers, Peter Marwedel: Algorithms for address assignment in DSP code generation. ICCAD 1996: 109-112 |
| c5 | | Rainer Leupers, Peter Marwedel: Instruction-Set Modeling for ASIP Code Generation. VLSI Design 1996: 77-80 |
| 1995 | ||
| c4 | | |
| 1994 | ||
| c3 | | Peter Marwedel, Rainer Leupers: Instruction set extraction from programmable structures. EURO-DAC 1994: 156-161 |
| c2 | | Rainer Leupers, Wolfgang Schenk, Peter Marwedel: Microcode Generation for Flexible Parallel Target Architectures. IFIP PACT 1994: 247-256 |
| 1993 | ||
| c1 | | |
Colors in the list of coauthors
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