David M. Lewis

David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu: Architectural enhancements in Stratix V™. FPGA 2013: 147-156

David M. Lewis, Vandana Pursnani Janeja: An Empirical Evaluation of Similarity Coefficients for Binary Valued Data. IJDWM 7(2): 44-66 (2011)

Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz: A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA 2010: 167-176

David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan: Architectural enhancements in Stratix-III^TM and Stratix-IV^TM. FPGA 2009: 33-42

David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20

Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144

David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose: The Stratix^TM routing and logic architecture. FPGA 2003: 12-20

Guy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28

Guy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131

Andy Ye, Jonathan Rose, David M. Lewis: Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT 2002: 219-226

Guy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68

L. Louis Zhang, Qiang Wang, David M. Lewis: Design of a VLIW Compute Accelerator on the Transmogrifier-2. FCCM 2000: 3-12

Guy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164

Andy Gean Ye, David M. Lewis: Procedural Texture Mapping on FPGAs. FPGA 1999: 112-120

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998)

Qiang Wang, David M. Lewis: Automated field-programmable compute accelerator design using partial evaluation. FCCM 1997: 145-154

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61

Vi Cuong Chan, David M. Lewis: Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. FPGA 1996: 51-57

David M. Lewis: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. Computers 43(8): 974-982 (1994)

Aditya A. Aggarwal, David M. Lewis: Routing Architectures for Hierarchical Field Programmable Gate Arrays. ICCD 1994: 475-478

Ahmet N. Parlakbilek, David M. Lewis: A multiple-strength multiple-delay compiled-code logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1937-1946 (1993)

David M. Lewis: An accurate LNS arithmetic unit using interleaved memory function interpolator. IEEE Symposium on Computer Arithmetic 1993: 2-9

David M. Lewis, Marcus van Ierssel, Daniel H. Wong: A Field Programmable Accelerator for Compiled-Code Applications. ICCD 1993: 491-496

David A. Johns, David M. Lewis, D. Cherepacha: Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. ISCAS 1993: 1302-1305

David M. Lewis: A compiled-code hardware accelerator for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 555-565 (1992)

Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White: Hector: A Hierarchically Structured Shared-memory Multiprocessor. IEEE Computer 24(1): 72-79 (1991)

David M. Lewis: A hierarchical compiled code event-driven logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 726-737 (1991)

David M. Lewis: An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. IEEE Trans. Computers 39(11): 1325-1336 (1990)

David M. Lewis: Device model approximation using 2^N trees. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 30-38 (1990)

Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis: Using Deducibility in Secure Network Modelling. ESORICS 1990: 117-123

David M. Lewis, Lawrence K. Yu: Algorithm design for a 30-bit integrated logarithmic processor. IEEE Symposium on Computer Arithmetic 1989: 192-199

David M. Lewis: Hardware accelerators for timing simulation of VLSI digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1134-1149 (1988)

David M. Lewis: A Programmable Hardware Accelerator for Compiled Electrical Simulation. DAC 1988: 172-177

David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson: Swamp: A Fast Processor for Smalltalk-80. OOPSLA 1986: 131-139

David M. Lewis: A hardware engine for analogue mode simulation of MOS digital circuits. DAC 1985: 345-351