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 | 2013 | |
|---|---|---|
| j22 |      | Song Jin, Yinhe Han, Huawei Li, Xiaowei Li: Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. IEEE Trans. VLSI Syst. 21(5): 821-833 (2013) |
| 2012 | ||
| j21 | | Xiang Fu, Huawei Li, Xiaowei Li: Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. VLSI Syst. 20(2): 236-247 (2012) |
| j20 | | Songwei Pei, Huawei Li, Xiaowei Li: A High-Precision On-Chip Path Delay Measurement Architecture. IEEE Trans. VLSI Syst. 20(9): 1565-1577 (2012) |
| j19 | | Songwei Pei, Huawei Li, Xiaowei Li: Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. IEEE Trans. VLSI Syst. 20(12): 2157-2169 (2012) |
| c54 | | Yuntan Fang, Huawei Li, Xiaowei Li: SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write. ATS 2012: 131-136 |
| 2011 | ||
| j18 | | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Transactions 94-D(4): 809-821 (2011) |
| j17 | | Song Jin, Yinhe Han, Huawei Li, Xiaowei Li: Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integration 44(3): 185-191 (2011) |
| j16 | | Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li: Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEE Trans. VLSI Syst. 19(10): 1787-1800 (2011) |
| j15 | | Minjin Zhang, Huawei Li, Xiaowei Li: Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. IEEE Trans. VLSI Syst. 19(11): 1969-1982 (2011) |
| c53 | | Yuntan Fang, Huawei Li, Xiaowei Li: A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. Asian Test Symposium 2011: 329-334 |
| c52 | | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li: Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE 2011: 968-973 |
| c51 | | Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li: An abacus turn model for time/space-efficient reconfigurable routing. ISCA 2011: 259-270 |
| c50 | | Songwei Pei, Huawei Li, Xiaowei Li: A unified test architecture for on-line and off-line delay fault detections. VTS 2011: 272-277 |
| 2010 | ||
| j14 | | Xiang Fu, Huawei Li, Xiaowei Li: Testable Critical Path Selection Considering Process Variation. IEICE Transactions 93-D(1): 59-67 (2010) |
| c49 | | Zijian He, Tao Lv, Huawei Li, Xiaowei Li: Graph partition based path selection for testing of small delay defects. ASP-DAC 2010: 499-504 |
| c48 | | Xiang Fu, Huawei Li, Xiaowei Li: On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. Asian Test Symposium 2010: 45-48 |
| c47 | | Song Jin, Yinhe Han, Huawei Li, Xiaowei Li: P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium 2010: 117-120 |
| c46 | | Zijian He, Tao Lv, Huawei Li, Xiaowei Li: An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium 2010: 319-324 |
| c45 | | Ying Zhang, Huawei Li, Xiaowei Li: Software-Based Self-Testing of Processors Using Expanded Instructions. Asian Test Symposium 2010: 415-420 |
| c44 | | Minjie Jin, Huawei Li, Yanhua Xiong, Jie Gao: The Application of the Optimum of MDOD in Structure Design of Double Reels for Wrapped Hoist. CASoN 2010: 675-678 |
| c43 | | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE 2010: 933-936 |
| c42 | | Songwei Pei, Huawei Li, Xiaowei Li: An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE 2010: 1353-1356 |
| c41 | | Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li: nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC 2010: 343-352 |
| c40 | | Zijian He, Tao Lv, Huawei Li, Xiaowei Li: On generation of a universal path candidate set containing testable long paths. ITC 2010: 816 |
| c39 | | Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li: Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC 2010: 70-76 |
| c38 | | Zijian He, Tao Lv, Huawei Li, Xiaowei Li: Fast path selection for testing of small delay defects considering path correlations. VTS 2010: 3-8 |
| 2009 | ||
| j13 | | Ying Zhang, Huawei Li, Xiaowei Li: Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. J. Comput. Sci. Technol. 24(6): 1074-1085 (2009) |
| j12 | | Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li: On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. VLSI Syst. 17(9): 1173-1186 (2009) |
| c37 | | Songwei Pei, Huawei Li, Xiaowei Li: A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium 2009: 145-150 |
| c36 | | Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu: A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium 2009: 219-224 |
| c35 | | Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan: M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium 2009: 437-442 |
| c34 | | Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang: Impact of Hazards on Pattern Selection for Small Delay Defects. PRDC 2009: 49-54 |
| c33 | | Li Liu, Jishun Kuang, Huawei Li: Small Delay Fault Simulation for Sequential Circuits. PRDC 2009: 63-68 |
| c32 | | Songwei Pei, Huawei Li, Xiaowei Li: Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC 2009: 75-80 |
| c31 | | Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC 2009: 276-281 |
| c30 | | Tao Lv, Huawei Li, Xiaowei Li: Automatic Selection of Internal Observation Signals for Design Verification. VTS 2009: 203-208 |
| 2008 | ||
| j11 | | Da Wang, Yu Hu, Huawei Li, Xiaowei Li: Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23(6): 1037-1046 (2008) |
| c29 | | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li: A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC 2008: 571-576 |
| c28 | | Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li: Robust test generation for power supply noise induced path delay faults. ASP-DAC 2008: 659-662 |
| c27 | | Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li: A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA 2008: 326-331 |
| c26 | | Minjin Zhang, Huawei Li, Xiaowei Li: Static Crosstalk Noise Analysis with Transition Map. DELTA 2008: 462-465 |
| c25 | | Hui Liu, Huawei Li, Yu Hu, Xiaowei Li: A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA 2008: 521-526 |
| c24 | | |
| c23 | | Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu: Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS 2008: 377-382 |
| c22 | | Minjin Zhang, Huawei Li, Xiaowei Li: Multiple Coupling Effects Oriented Path Delay Test Generation. VTS 2008: 383-388 |
| 2007 | ||
| j10 | | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) |
| c21 | | Lei Zhang, Huawei Li, Xiaowei Li: A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) 2007: 1210-1219 |
| c20 | | Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li: Bug analysis and corresponding error models in real designs. HLDVT 2007: 59-64 |
| c19 | | Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li: The design-for-testability features of a general purpose microprocessor. ITC 2007: 1-9 |
| 2006 | ||
| j9 | | Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra: Response compaction for system-on-a-chip based on advanced convolutional codes. Science in China Series F: Information Sciences 49(2): 262-272 (2006) |
| j8 | | Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006) |
| j7 | | Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE T. Instrumentation and Measurement 55(2): 389-399 (2006) |
| c18 | | |
| c17 | | Huawei Li, Yu Fan, Tao Wu: Impact of Load Characteristics and Low-Voltage Load Shedding Schedule on Dynamic Voltage Stability. CCECE 2006: 2249-2252 |
| c16 | | Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han: Fast Packet Classification using Group Bit Vector. GLOBECOM 2006 |
| c15 | | Huawei Li, Pei-Fu Shen, Xiaowei Li: Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS 2006: 300-305 |
| 2005 | ||
| j6 | | Huawei Li, Xiaowei Li: Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electronic Testing 21(2): 181-195 (2005) |
| j5 | | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005) |
| j4 | | Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005) |
| j3 | | Shuguang Gong, Huawei Li, Xiaowei Li: An innovative free memory design for network processors in home network gateway. IEEE Trans. Consumer Electronics 51(4): 1182-1187 (2005) |
| c14 | | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58 |
| c13 | | Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li: Design of an efficient memory subsystem for network processor. ASP-DAC 2005: 897-900 |
| c12 | | Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li: Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium 2005: 120-125 |
| c11 | | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243 |
| c10 | | Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 |
| 2004 | ||
| c9 | | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 |
| c8 | | Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li: Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 |
| c7 | | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 |
| 2003 | ||
| j2 | | Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li: A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. 18(3): 308-317 (2003) |
| c6 | | Huawei Li, Yue Zhang, Xiaowei Li: Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium 2003: 178-183 |
| c5 | | Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445 |
| 2002 | ||
| c4 | | Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min: Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium 2002: 332-337 |
| 2001 | ||
| c3 | | Huawei Li, Yinghua Min, Zhongcheng Li: An RT-Level ATPG Based on Clustering of Circuit States. Asian Test Symposium 2001: 213-218 |
| c2 | | Xiaowei Li, Huawei Li, Yinghua Min: Reducing Power Dissipation during At-Speed Test Application. DFT 2001: 116- |
| 2000 | ||
| j1 | | Huawei Li, Zhongcheng Li, Yinghua Min: Reduction of Number of Paths to be Tested in Delay Testing. J. Electronic Testing 16(5): 477-485 (2000) |
| 1998 | ||
| c1 | | Huawei Li, Zhongcheng Li, Yinghua Min: Delay Testing with Double Observations. Asian Test Symposium 1998: 96- |
Colors in the list of coauthors
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