John Lillis

Hosung Kim, John Lillis: A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2120-2132 (2008)

Hosung (Leo) Kim, John Lillis: A framework for layout-level logic restructuring. ISPD 2008: 87-94

Devang Jariwala, John Lillis: RBI: Simultaneous Placement and Routing Optimization Technique. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 127-141 (2007)

Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis: Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. ASP-DAC 2007: 609-615

Salim Chowdhury, John Lillis: Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. ISPD 2007: 59-66

Milos Hrkic, John Lillis, Giancarlo Beraudo: An Approach to Placement-Coupled Logic Replication. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2539-2551 (2006)

Hosung (Leo) Kim, John Lillis, Milos Hrkic: Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI 2006: 211-216

Devang Jariwala, John Lillis: Trunk decomposition based global routing optimization. ICCAD 2006: 472-479

Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal: An LP-based methodology for improved timing-driven placement. ASP-DAC 2005: 1139-1143

Qingzhou (Ben) Wang, Devang Jariwala, John Lillis: A study of tighter lower bounds in LP relaxation based placement. ACM Great Lakes Symposium on VLSI 2005: 498-502

Milos Hrkic, John Lillis, Giancarlo Beraudo: An approach to placement-coupled logic replication. DAC 2004: 711-716

Devang Jariwala, John Lillis: On interactions between routing and detailed placement. ICCAD 2004: 387-393

Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 481-491 (2003)

Giancarlo Beraudo, John Lillis: Timing optimization of FPGA placements by logic replication. DAC 2003: 196-201

Ashok Jagannathan, Sung-Woo Hur, John Lillis: A fast algorithm for context-aware buffer insertion. ACM Trans. Design Autom. Electr. Syst. 7(1): 173-188 (2002)

Milos Hrkic, John Lillis: S-Tree: a technique for buffered routing tree synthesis. DAC 2002: 578-583

Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. ISPD 2002: 98-103

David P. LaPotin, Charles J. Alpert, John Lillis (Eds.): Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002. ACM 2002, isbn 1-58113-526-2

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9

Sung-Woo Hur, Ashok Jagannathan, John Lillis: Timing-driven maze routing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 234-241 (2000)

Ashok Jagannathan, Sung-Woo Hur, John Lillis: A fast algorithm for context-aware buffer insertion. DAC 2000: 368-373

Sung-Woo Hur, John Lillis: MONGREL: Hybrid Techniques for Standard Cell Placement. ICCAD 2000: 165-170

John Lillis, Chung-Kuan Cheng: Timing optimization for multisource nets: characterization andoptimal repeater insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 322-331 (1999)

Sung-Woo Hur, John Lillis: Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. DAC 1999: 360-366

Sung-Woo Hur, Ashok Jagannathan, John Lillis: Timing driven maze routing. ISPD 1999: 208-213

John Lillis, Premal Buch: Table-Lookup Methods for Improved Performance-Driven Routing. DAC 1998: 368-373

Fang-Jou Liu, John Lillis, Chung-Kuan Cheng: A new layout-driven timing model for incremental layout optimization. ASP-DAC 1997: 127-131

John Lillis, Chung-Kuan Cheng: Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. DAC 1997: 214-219

Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng: New Spectral Linear Placement and Clustering Approach. DAC 1996: 88-93

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho: New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143

Jianmin Li, John Lillis, Chung-Kuan Cheng: Linear decomposition algorithm for VLSI design applications. ICCAD 1995: 223-228