Sung Kyu Lim

Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim: Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. IEEE Trans. VLSI Syst. 21(5): 862-874 (2013)

Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim: High-density integration of functional modules using monolithic 3D-IC technology. ASP-DAC 2013: 681-686

Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim: Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. ASP-DAC 2013: 687-692

Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim: Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. ASP-DAC 2013: 693-698

Dae Hyun Kim, Sung Kyu Lim: Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 240-248 (2012)

Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, Linda Milor: Backend dielectric reliability simulator for microprocessor system. Microelectronics Reliability 52(9-10): 1953-1959 (2012)

Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim: TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1194-1207 (2012)

Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim: Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1222-1234 (2012)

Michael B. Healy, Sung Kyu Lim: Distributed TSV Topology for 3-D Power-Supply Networks. IEEE Trans. VLSI Syst. 20(11): 2066-2079 (2012)

Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim: Block-level 3D IC design with through-silicon-via planning. ASP-DAC 2012: 335-340

Xin Zhao, Sung Kyu Lim: Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. ASP-DAC 2012: 347-352

David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang: Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755

Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, Sung Kyu Lim: TSV Stress-Aware ATPG for 3D Stacked ICs. ATS 2012: 31-36

Young-Joon Lee, Inki Hong, Sung Kyu Lim: Slew-aware buffer insertion for through-silicon-via-based 3D ICs. CICC 2012: 1-8

Xin Zhao, Michael Scheuermann, Sung Kyu Lim: Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. DAC 2012: 157-162

Moongon Jung, David Z. Pan, Sung Kyu Lim: Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. DAC 2012: 317-326

Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim: Exploiting die-to-die thermal coupling in 3D IC placement. DAC 2012: 741-746

Jiwoo Pak, Sung Kyu Lim, David Z. Pan: Electromigration-aware routing for 3D ICs with stress-aware EM modeling. ICCAD 2012: 325-332

Young-Joon Lee, Patrick Morrow, Sung Kyu Lim: Ultra high density logic designs using transistor-level monolithic 3D integration. ICCAD 2012: 539-546

Xin Zhao, Sung Kyu Lim: TSV array utilization in low-power 3D clock network design. ISLPED 2012: 21-26

Young-Joon Lee, Sung Kyu Lim: Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects. ISQED 2012: 228-335

Chang Liu, Sung Kyu Lim: A design tradeoff study with monolithic 3D integration. ISQED 2012: 529-536

Kaiyuan Yang, Dae Hyun Kim, Sung Kyu Lim: Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices. ISQED 2012: 740-746

Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim: 3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190

Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim: Scan test of die logic in 3D ICs using TSV probing. ITC 2012: 1-8

Shreepad Panth, Sung Kyu Lim: Transition delay fault testing of 3D ICs with IR-drop study. VTS 2012: 270-275

Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim: Impact of irregular geometries on low-k dielectric breakdown. Microelectronics Reliability 51(9-11): 1582-1586 (2011)

Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim: Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 732-745 (2011)

Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay: Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1349-1358 (2011)

Young-Joon Lee, Sung Kyu Lim: Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1635-1648 (2011)

Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim: Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. ACM Trans. Design Autom. Electr. Syst. 16(4): 46 (2011)

Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan: Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626

Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. DAC 2011: 188-193

Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim: Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. DAC 2011: 783-788

Michael B. Healy, Sung Kyu Lim: A novel TSV topology for many-tier 3D power-delivery networks. DATE 2011: 261-264

Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim: Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. ICCAD 2011: 555-562

Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim: Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. ICCAD 2011: 563-570

Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, Hsien-Hsin S. Lee: Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD 2011: 90-95

Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim: Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. ISLPED 2011: 9-14

Chang Liu, Taigon Song, Sung Kyu Lim: Signal integrity analysis and optimization for 3D ICs. ISQED 2011: 42-49

Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon: Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ISQED 2011: 122-128

Michael B. Healy, Sung Kyu Lim: Power-supply-network design in 3D integrated systems. ISQED 2011: 223-228

Daehyun Kim, Suyoun Kim, Sung Kyu Lim: Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs. SLIP 2011: 1-8

Shreepad Panth, Sung Kyu Lim: Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. VTS 2011: 26-31

Jae Sub Oh, Kwang Il Choi, Young Su Kim, Min Ho Kang, Myeong Ho Song, Sung Kyu Lim, Dong Eun Yoo, Jeong Gyu Park, Hi Deok Lee, Ga Won Lee: SONOS-Type Flash Memory with HfO₂ Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition. IEICE Transactions 93-C(5): 590-595 (2010)

Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim: Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. Microelectronics Reliability 50(9-11): 1341-1346 (2010)

Moongon Jung, Sung Kyu Lim: A study of IR-drop noise issues in 3D ICs with through-silicon-vias. 3DIC 2010: 1-7

Young-Joon Lee, Sung Kyu Lim: Timing analysis and optimization for 3D stacked multi-core microprocessors. 3DIC 2010: 1-7

Xin Zhao, Sung Kyu Lim: Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. ASP-DAC 2010: 175-180

Krit Athikulwongse, Xin Zhao, Sung Kyu Lim: Buffered clock tree sizing for skew minimization under power and thermal budgets. ASP-DAC 2010: 474-479

Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim: Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4

Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan: TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806

Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim: Through-silicon-via management during 3D physical design: When to add and how many? ICCAD 2010: 387-394

Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674

Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay: Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. ICCAD 2010: 694-697

Daehyun Kim, Sung Kyu Lim: Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. SLIP 2010: 25-32

Mohit Pathak, Sung Kyu Lim: Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1373-1386 (2009)

I. Faik Baskaya, David V. Anderson, Sung Kyu Lim: Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing. IEEE Trans. on Circuits and Systems 56-II(7): 565-569 (2009)

Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim: Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC 2009: 43-48

Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad S. Bakir, Yogendra Joshi, Andrei Fedorov, Sung Kyu Lim: Co-design of signal, power, and thermal distribution networks for 3D ICs. DATE 2009: 610-615

Ye Tao, Sung Kyu Lim: Decoupling capacitor planning with analytical delay model on RLC power grid. DATE 2009: 839-844

Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim: Pre-bond testable low-power clock tree design for 3D stacked ICs. ICCAD 2009: 184-190

Young-Joon Lee, Rohan Goel, Sung Kyu Lim: Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. ICCAD 2009: 645-651

Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim: A study of Through-Silicon-Via impact on the 3D stacked IC layout. ICCAD 2009: 674-680

Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay: Slew-aware clock tree design for reliable subthreshold circuits. ISLPED 2009: 15-20

Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim: Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. SLIP 2009: 85-92

Dae Hyun Kim, Sung Kyu Lim: Bus-aware microarchitectural floorplanning. ASP-DAC 2008: 204-208

Jacob R. Minz, Xin Zhao, Sung Kyu Lim: Buffered clock tree synthesis for 3D ICs under thermal variations. ASP-DAC 2008: 504-509

Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim: A unified methodology for power supply noise reduction in modern microarchitecture design. ASP-DAC 2008: 611-616

Dae Hyun Kim, Sung Kyu Lim: Global bus route optimization with application to microarchitectural design exploration. ICCD 2008: 658-663

Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh: Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 38-52 (2007)

Eric Wong, Jacob R. Minz, Sung Kyu Lim: Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2023-2034 (2007)

Sung Kyu Lim, Massoud Pedram: Introduction to special issue on demonstrable software systems and hardware platforms. ACM Trans. Design Autom. Electr. Syst. 12(3) (2007)

Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim: An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. ASP-DAC 2007: 547-552

Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee: Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. ASP-DAC 2007: 786-791

I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler: Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. FCCM 2007: 319-320

Mohit Pathak, Sung Kyu Lim: Thermal-aware Steiner routing for 3D stacked ICs. ICCAD 2007: 205-211

Eric Wong, Sung Kyu Lim: Whitespace redistribution for thermal via insertion in 3D stacked ICs. ICCD 2007: 267-272

Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim: Placement and routing of RF embedded passive designs in LCP substrate. ICCD 2007: 273-279

Peter G. Sassone, Sung Kyu Lim: Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1075-1086 (2006)

Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim: Profile-guided microarchitectural floor planning for deep submicron processor design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1289-1300 (2006)

Jacob R. Minz, Sung Kyu Lim: Block-level 3-D Global Routing With an Application to 3-D Packaging. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2248-2257 (2006)

Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim: Profile-Driven Instruction Mapping for Dataflow Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3017-3025 (2006)

Eric Wong, Jacob R. Minz, Sung Kyu Lim: Multi-Objective Module Placement For 3-D System-On-Package. IEEE Trans. VLSI Syst. 14(5): 553-557 (2006)

I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson: Placement for large-scale floating-gate field-programable analog arrays. IEEE Trans. VLSI Syst. 14(8): 906-910 (2006)

Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim: Statistical Bellman-Ford algorithm with an application to retiming. ASP-DAC 2006: 959-964

Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim: Optical routing for 3D system-on-package. DATE 2006: 337-338

Eric Wong, Sung Kyu Lim: 3D floorplanning with thermal vias. DATE 2006: 878-883

Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh: Microarchitectural floorplanning under performance and thermal tradeoff. DATE 2006: 1288-1293

Eric Wong, Jacob R. Minz, Sung Kyu Lim: Decoupling capacitor planning and sizing for noise and leakage reduction. ICCAD 2006: 395-400

Mongkol Ekpanyapong, Sung Kyu Lim: Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. ISPD 2006: 142-148

Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee: A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. MICRO 2006: 3-14

Sung Kyu Lim: Physical Design for 3D System on Package. IEEE Design & Test of Computers 22(6): 532-539 (2005)

Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier: Automatic cell placement for quantum-dot cellular automata. Integration 38(3): 541-548 (2005)

Sung Kyu Lim, Ramprasad Ravichandran, Michael T. Niemier: Partitioning and placement for buildable QCA circuits. JETC 1(1): 50-72 (2005)

Ramprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim: Partitioning and placement for buildable QCA circuits. ASP-DAC 2005: 424-427

Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim: Placement for configurable dataflow architecture. ASP-DAC 2005: 1127-1130

Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim: Wire congestion and thermal aware 3D global placement. ASP-DAC 2005: 1131-1134

Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim: MILP-based Placement and Routing for Dataflow Architecture. FPL 2005: 71-76

I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson: Hierarchical Placement for Large-scale FPAA. FPL 2005: 421-426

Brian Stephen Smith, Sung Kyu Lim: QCA channel routing with wire crossing minimization. ACM Great Lakes Symposium on VLSI 2005: 217-220

Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh: 3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461

Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee: Wire-driven microarchitectural design space exploration. ISCAS (2) 2005: 1867-1870

I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson S. Hall, David V. Anderson: Mapping algorithm for large-scale field programmable analog array. ISPD 2005: 152-158

Jacob R. Minz, Eric Wong, Sung Kyu Lim: Reliability-aware floorplanning for 3D circuits. SoCC 2005: 81-82

Jason Cong, Sung Kyu Lim: Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 346-357 (2004)

Jason Cong, Sung Kyu Lim: Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1684-1692 (2004)

Jacob R. Minz, Sung Kyu Lim: Layer assignment for reliable system-on-package. ASP-DAC 2004: 31-37

Mongkol Ekpanyapong, Sung Kyu Lim: Performance-driven global placement via adaptive network characterization. ASP-DAC 2004: 137-142

Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim: Profile-guided microarchitectural floorplanning for deep submicron processor design. DAC 2004: 634-639

Jacob R. Minz, Mohit Pathak, Sung Kyu Lim: Net and Pin Distribution for 3D Package Global Routing. DATE 2004: 1410-1411

Ramprasad Ravichandran, Nihal Ladiwala, Jean Nguyen, Michael T. Niemier, Sung Kyu Lim: Automatic cell placement for quantum-dot cellular automata. ACM Great Lakes Symposium on VLSI 2004: 332-337

Mongkol Ekpanyapong, Karthik Balakrishnan, Vidit Nanda, Sung Kyu Lim: Simultaneous delay and power optimization in global placement. ISCAS (5) 2004: 57-60

Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, Sung Kyu Lim: Multi-layer floorplanning for reliable system-on-package. ISCAS (5) 2004: 69-72

Peter G. Sassone, Sung Kyu Lim: A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. ICCAD 2003: 74-80

Jason Cong, Sung Kyu Lim: Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC 2000: 429-434

Jason Cong, Sung Kyu Lim: Performance driven multiway partitioning. ASP-DAC 2000: 441-446

Jason Cong, Sung Kyu Lim, Chang Wu: Performance driven multi-level and multiway partitioning with retiming. DAC 2000: 274-279

Jason Cong, Sung Kyu Lim: Physical Planning with Retiming. ICCAD 2000: 2-7

Jason Cong, Sung Kyu Lim: Multiway partitioning with pairwise movement. ICCAD 1998: 512-516

Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu: Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD 1997: 441-446