Kuan Jen Lin

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	2011
c9		Kuan Jen Lin, Chih Ping Weng, Tsai Kun Hou: Enhance hardware security using FIFO in pipelines. IAS 2011: 344-349
	2010
c8		Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin: A decimal squarer with efficient partial product generation. VLSI-SoC 2010: 213-218
	2009
c7		Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang: Design Optimization and Automation for Secure Cryptographic Circuits. VLSI Design 2009: 321-326
	2007
c6		Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo: Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. DATE 2007: 1265-1270
c5		Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen: Optimal Allocation of I/O Device Parameters in Hardware and Software Codesign Methodology. EUC 2007: 541-552
	2006
c4		Kuan Jen Lin, Chuang Hsiang Huang, Cheng Chia Lo: Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform. APCCAS 2006: 279-282
c3		Kuan Jen Lin, Shih Hao Huang, Shan Chien Fang: Cooptimization of interface hardware and software for I/O controllers. DATE 2006: 724-725
	2005
c2		Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen: A hardware/software codesign approach for programmable IO devices. ACM Great Lakes Symposium on VLSI 2005: 323-327
	2004
c1		Kuan Jen Lin, Shih Wen Chen: On the formulation of software cost for IO devices. IASTED Conf. on Software Engineering and Applications 2004: 761-766

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