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Tay-Jyi Lin
2010 – today
- 2013
[c32]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang: A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159- 2012
- [j7]Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu: A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. on Circuits and Systems 59-II(12): 908-912 (2012)
- [c31]Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh: Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. ASP-DAC 2012: 473-474
- [c30]Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu: Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC 2012: 477-478
- [c29]Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu: A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS 2012: 1335-1338
- 2011
- [j6]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu: Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Sig. Proc. 2011 (2011)
- [j5]Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin: Hierarchical circuit-switched NoC for multicore video processing. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 182-199 (2011)
- [j4]David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu: Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. Signal Processing Systems 62(3): 373-382 (2011)
- 2010
- [j3]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu: Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. on Circuits and Systems 57-I(7): 1684-1696 (2010)
- [c28]Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin: RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE 2010: 287-290
- [c27]Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu: Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI 2010: 347-352
- [c26]Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang: Hierarchical memory scheduling for multimedia MPSoCs. ICCAD 2010: 190-196
- [c25]Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu: Complexity-effective dynamic range compression for digital hearing aids. ISCAS 2010: 2378-2381
- [c24]Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu: Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS 2010: 4165-4168
2000 – 2009
- 2009
- [c23]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu: Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC 2009: 115-116
- [c22]Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu: Parallel object detection on multicore platforms. SiPS 2009: 075-080
- 2008
- [j2]Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao: Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. Signal Processing Systems 51(3): 209-223 (2008)
- [c21]Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu: Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC 2008: 115-116
- [c20]Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu: Cycle Stealing and Channel Management for On-Chip Networks. HPCC 2008: 53-60
- [c19]Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young: Complexity-effective auditory compensation for digital hearing aids. ISCAS 2008: 1472-1475
- [c18]Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu: Improving datapathutilization of programmable DSP with composite functional units. ISCAS 2008: 3438-3441
- 2007
- [c17]Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu: Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC 2007: 110-111
- [c16]Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu: Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS 2007: 409-412
- [c15]Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen: Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS 2007: 3506-3509
- 2006
- [j1]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen: A Compact DSP Core with Static Floating-Point Arithmetic. VLSI Signal Processing 42(2): 127-138 (2006)
- [c14]Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen: A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC 2006: 118-119
- [c13]Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen: Programmable FIR filter with adder-based computing engine. ISCAS 2006
- 2005
- [c12]Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen: A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55
- [c11]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen: Architecture for area-efficient 2-D transform in H.264/AVC. ICME 2005: 1126-1129
- [c10]Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen: Pipelining technique for energy-aware datapaths. ISCAS (2) 2005: 1218-1221
- [c9]Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen: Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) 2005: 3503-3506
- 2004
- [c8]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen: A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI 2004: 57-60
- [c7]Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen: Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) 2004: 821-824
- 2003
- [c6]Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen: An Efficient VLIW DSP Architecture for Baseband Processing. ICCD 2003: 307-312
- [c5]Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen: Performance evaluation of ring-structure register file in multimedia applications. ICME 2003: 121-124
- [c4]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen: Coefficient optimization for area-effective multiplier-less FIR filters. ICME 2003: 125-128
- [c3]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen: Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) 2003: 173-176
- 2002
- [c2]Tay-Jyi Lin, Chein-Wei Jen: CASCADE - configurable and scalable DSP environment. ISCAS (4) 2002: 870-873
- 2001
- [c1]Tay-Jyi Lin, Chein-Wei Jen: An efficient 2-D DWT architecture via resource cycling. ISCAS (4) 2001: 914-917
Coauthor Index
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last updated on 2013-04-09 21:24 CEST by the dblp team