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 | 2012 | |
|---|---|---|
| j7 |      | Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee: Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). J. Solid-State Circuits 47(11): 2551-2553 (2012) |
| c8 | | Chun-Hong Lee, Hung-Chang Jau, Shih-Hui Chang, Tsung-Hsien Lin: Simulation of laser phenomenon of cholesteric liquid crystal using axuillary differential equation finite-difference time-domain method. WOCC 2012: 180-182 |
| c7 | | Hung-Chang Jau, Tsung-Hsien Lin, Yan-Yu Chen, Chun-Wei Chen, Jui-Hsiang Liu, Andy Y.-G. Fuh: Electrical and optical switchings of the direcitons of cholesteric liquid crystals gratings. WOCC 2012: 183-185 |
| 2011 | ||
| j6 | | Chen-Yen Ho, Wei-Shan Chan, Yung-Yu Lin, Tsung-Hsien Lin: A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. J. Solid-State Circuits 46(11): 2571-2582 (2011) |
| j5 | | Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin: A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation. IEEE Trans. on Circuits and Systems 58-II(12): 867-871 (2011) |
| j4 | | Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, Yu-Hsiang Huang: A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. IEEE Trans. VLSI Syst. 19(4): 585-591 (2011) |
| 2010 | ||
| j3 | | Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin: A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. J. Solid-State Circuits 45(6): 1137-1149 (2010) |
| j2 | | Yao-Hong Liu, Tsung-Hsien Lin: A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers. J. Solid-State Circuits 45(10): 2066-2079 (2010) |
| c6 | | Chen-Yen Ho, Yung-Yu Lin, Tsung-Hsien Lin: Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. ISCAS 2010: 25-28 |
| c5 | | Wei-Hao Chiu, Chien-Yuan Cheng, Tsung-Hsien Lin: A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. ISCAS 2010: 2996-2999 |
| 2009 | ||
| j1 | | Tsung-Hsien Lin, Ching-Lung Ti, Yao-Hong Liu: Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- N PLLs. IEEE Trans. on Circuits and Systems 56-I(5): 877-885 (2009) |
| 2008 | ||
| c4 | | Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin: A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. ISCAS 2008: 1728-1731 |
| 2006 | ||
| c3 | | Wai-Chi Fang, Tsung-Hsien Lin: Low-Power Radio Design for Wireless Smart Sensor Networks. IIH-MSP 2006: 583-586 |
| 1999 | ||
| c2 | | Razieh Rofougaran, Tsung-Hsien Lin, William J. Kaiser: CMOS front-end LNA-mixer of micropower RF wireless systems. ISLPED 1999: 238-242 |
| 1998 | ||
| c1 | | Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser: CMOS front end components for micropower RF wireless systems. ISLPED 1998: 11-15 |
Colors in the list of coauthors
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