Ying-Zu Lin

Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang: A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE Trans. on Circuits and Systems 60-I(3): 570-581 (2013)

Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin: 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. VLSI Syst. 21(3): 584-588 (2013)

Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang: Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. VLSI Syst. 21(4): 624-635 (2013)

Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang: A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. IEICE Transactions 95-A(12): 2415-2423 (2012)

Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin: A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. J. Solid-State Circuits 47(11): 2783-2795 (2012)

Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin: A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. J. Solid-State Circuits 45(4): 731-740 (2010)

Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang: An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. on Circuits and Systems 57-I(8): 1829-1837 (2010)

Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang: A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. VLSI Syst. 18(3): 509-513 (2010)

Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai: A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC 2010: 386-387

Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu: A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. IEICE Transactions 92-C(2): 258-268 (2009)

Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang: A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC 2009: 80-81

Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu: A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. IEEE Trans. on Circuits and Systems 55-II(11): 1089-1093 (2008)