Loganathan Lingappan

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram: A Novel SMT-Based Technique for LFSR Reseeding. VLSI Design 2012: 394-399

Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram: A SMT-based diagnostic test generation method for combinational circuits. VTS 2012: 215-220

Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan: Strategies for scalable symbolic execution-driven test generation for programs. SCIENCE CHINA Information Sciences 54(9): 1797-1812 (2011)

Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy: An Efficient 2-Phase Strategy to Achieve High Branch Coverage. Asian Test Symposium 2011: 167-174

Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan: Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. Asian Test Symposium 2010: 59-64

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty: Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. VLSI Syst. 17(5): 697-708 (2009)

Loganathan Lingappan, Niraj K. Jha: Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1339-1345 (2007)

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. VLSI Syst. 15(1): 24-36 (2007)

Loganathan Lingappan, Niraj K. Jha: Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. VLSI Syst. 15(5): 518-530 (2007)

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha: Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design 2007: 504-512

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha: Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 544-557 (2006)

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006)

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: Test generation for combinational quantum cellular automata (QCA) circuits. DATE 2006: 311-316

Loganathan Lingappan, Niraj K. Jha: Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design 2006: 431-436

Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar: Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70

Loganathan Lingappan, Niraj K. Jha: Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS 2005: 418-423

Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha: Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD 2003: 187-193