C. L. Liu

Chung Laung (Dave) Liu

劉炯朗

	2012
j50		D. Li, X. L. Sun, C. L. Liu: An exact solution method for unconstrained quadratic 0-1 programming: a geometric approach. J. Global Optimization 52(4): 797-829 (2012)
j49		X. L. Sun, C. L. Liu, D. Li, J. J. Gao: On duality gap in binary quadratic programming. J. Global Optimization 53(2): 255-269 (2012)
c67		C. L. Liu: I attended the nineteenth design automation conference. ISPD 2012: 69-70
	2005
c66		C. L. Liu: The High Walls have Crumpled. VLSI Design 2005: 21-
	2003
j48		Ali Pinar, C. L. Liu: Compacting sequences with invariant transition frequencies. ACM Trans. Design Autom. Electr. Syst. 8(2): 214-221 (2003)
j47		Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. VLSI Syst. 11(1): 79-89 (2003)
j46		Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang: Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. VLSI Syst. 11(5): 879-887 (2003)
	2002
j45		Ki-Seok Chung, Taewhan Kim, C. L. Liu: A Complete Model for Glitch Analysis in Logic Circuits. Journal of Circuits, Systems, and Computers 11(2): 137-154 (2002)
j44		Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang: Domino logic synthesis based on implication graph. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 232-240 (2002)
j43		Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
j42		Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu: Synthesis and Optimization of Combinational Interface Circuits. VLSI Signal Processing 31(3): 243-261 (2002)
c65		Shih-Liang Chen, TingTing Hwang, C. L. Liu: A technology mapping algorithm for CPLD architectures. FPT 2002: 204-210
	2001
j41		Prashant Saxena, C. L. Liu: Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 503-515 (2001)
j40		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. IEEE Trans. VLSI Syst. 9(2): 383-389 (2001)
j39		Ki-Seok Chung, Taewhan Kim, C. L. Liu: G-vector: A New Model for Glitch Analysis in Logic Circuits. VLSI Signal Processing 27(3): 235-251 (2001)
c64		Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737
c63		Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu: Binary decision diagram with minimum expected path length. DATE 2001: 708-712
	2000
j38		Prashant Saxena, C. L. Liu: A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 691-702 (2000)
c62		Junhyung Um, Taewhan Kim, C. L. Liu: A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103
c61		Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321
c60		Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang: Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
	1999
j37		Peichen Pan, C. L. Liu: Partial Scan with Preselected Scan Signals. IEEE Trans. Computers 48(9): 1000-1005 (1999)
c59		Prashant Saxena, C. L. Liu: Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103
c58		Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162
c57		Ki-Wook Kim, C. L. Liu, Sung-Mo Kang: Implication graph based domino logic synthesis. ICCAD 1999: 111-114
c56		Junhyung Um, Taewhan Kim, C. L. Liu: Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413
c55		Chaeryung Park, Taewhan Park, C. L. Liu: An efficient data path synthesis algorithm for behavioral-level power optimization. ISCAS (1) 1999: 294-297
c54		C. L. Liu: From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. RTSS 1999: 5
c53		Prashant Saxena, Peichen Pan, C. L. Liu: The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407
	1998
j36		Peichen Pan, Arvind K. Karandikar, C. L. Liu: Optimal clock period clustering for sequential circuits with retiming. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 489-498 (1998)
j35		Peichen Pan, C. L. Liu: Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans. Design Autom. Electr. Syst. 3(3): 437-462 (1998)
j34		Chaeryung Park, Taewhan Kim, C. L. Liu: Register Allocation - A Hierarchical Reduction Approach. VLSI Signal Processing 19(3): 269-285 (1998)
c52		Prashant Saxena, C. L. Liu: A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127
c51		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. ICCAD 1998: 408-411
c50		Ali Pinar, C. L. Liu: Power invariant vector sequence compaction. ICCAD 1998: 473-476
c49		Unni Narayanan, Peichen Pan, C. L. Liu: Low power logic synthesis under a general delay model. ISLPED 1998: 209-214
c48		Ki-Seok Chung, C. L. Liu: Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. ISLPED 1998: 215-220
	1997
j33		Peichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. Algorithmica 18(4): 560-574 (1997)
j32		Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 20-31 (1997)
j31		Anmol Mathur, C. L. Liu: Timing-driven placement for regular architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 597-608 (1997)
c47		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661
c46		Unni Narayanan, C. L. Liu: Low power logic synthesis for XOR based circuits. ICCAD 1997: 570-574
c45		Arvind K. Karandikar, Peichen Pan, C. L. Liu: Optimal Clock Period Clustering for Sequential Circuits with Retiming. ICCD 1997: 122-127
	1996
j30		Peichen Pan, Weiping Shi, C. L. Liu: Area Minimization for Hierarchical Floorplans. Algorithmica 15(6): 550-571 (1996)
j29		Tong Gao, C. L. Liu: Minimum crosstalk channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 465-474 (1996)
j28		Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu: Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996)
j27		Taewhan Kim, C. L. Liu: An integrated algorithm for incremental data path synthesis. VLSI Signal Processing 12(3): 265-285 (1996)
c44		Peichen Pan, C. L. Liu: Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. DAC 1996: 720-725
c43		Xiangfeng Chen, Peichen Pan, C. L. Liu: Desensitization for Power Reduction in Sequential Circuits. DAC 1996: 795-800
c42		Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu: A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831
c41		Peichen Pan, C. L. Liu: Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. FPGA 1996: 58-64
c40		Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu: An algorithm for synthesis of system-level interface circuits. ICCAD 1996: 442-447
	1995
j26		Taewhan Kim, C. L. Liu: A new approach to the multiport memory allocation problem in data path synthesis. Integration 19(3): 133-160 (1995)
j25		Tong Gao, C. L. Liu: Minimum crosstalk switchbox routing. Integration 19(3): 161-180 (1995)
j24		Peichen Pan, C. L. Liu: Area minimization for floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 123-132 (1995)
j23		Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu: Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. IEEE Trans. Parallel Distrib. Syst. 6(5): 498-511 (1995)
c39		Peichen Pan, C. L. Liu: Partial Scan with Pre-selected Scan Signals. DAC 1995: 189-194
c38		Anmol Mathur, K. C. Chen, C. L. Liu: Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124
c37		Anmol Mathur, K. C. Chen, C. L. Liu: Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490
	1994
j22		Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu: A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 425-438 (1994)
c36		Yachyang Sun, C. L. Liu: Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. DAC 1994: 171-176
c35		Srilata Raman, C. L. Liu, Larry G. Jones: A delay driven FPGA placement algorithm. EURO-DAC 1994: 277-282
c34		Anmol Mathur, C. L. Liu: Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD 1994: 130-136
c33		Peichen Pan, Weiping Shi, C. L. Liu: Area minimization for hierarchical floorplans. ICCAD 1994: 436-440
c32		Tong Gao, C. L. Liu: Minimum crosstalk switchbox routing. ICCAD 1994: 610-615
	1993
j21		Jason Cong, Bryan Preas, C. L. Liu: Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 723-734 (1993)
j20		Wei-Kuan Shih, Jane W.-S. Liu, C. L. Liu: Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. IEEE Trans. Software Eng. 19(12): 1171-1179 (1993)
c31		Taewhan Kim, C. L. Liu: Utilization of Multiport Memories in Data Path Synthesis. DAC 1993: 298-302
c30		Peichen Pan, Sai-keung Dong, C. L. Liu: Optimal Graph Constraint Reduction for Symbolic Layout Compaction. DAC 1993: 401-406
c29		Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu: Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490
c28		Tong Gao, C. L. Liu: Minimum crosstalk channel routing. ICCAD 1993: 692-696
	1992
c27		Tong Gao, Pravin M. Vaidya, C. L. Liu: A Performance Driven Macro-Cell Placement Algorithm. DAC 1992: 147-152
c26		Peichen Pan, C. L. Liu: Area minimization for general floorplans. ICCAD 1992: 606-609
c25		Yachyang Sun, C. L. Liu: An Area Minimizer for Floorplans with L-Shaped Regions. ICCD 1992: 383-386
	1991
j19		Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu: Disjoint Covers in Replicated Heterogeneous Arrays. SIAM J. Discrete Math. 4(2): 281-292 (1991)
j18		Jason Cong, C. L. Liu: On the k-layer planar subset and topological via minimization problems. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 972-981 (1991)
c24		Tong Gao, Pravo M. Vaidya, C. L. Liu: A New Performance Driven Placement Algorithm. ICCAD 1991: 44-47
c23		Taewhan Kim, Jane W.-S. Liu, C. L. Liu: A Scheduling Algorithm for Conditional Resource Sharing. ICCAD 1991: 84-87
c22		Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu: A Channel Router for Single Layer Customization Technology. ICCAD 1991: 436-439
	1990
j17		Jason Cong, C. L. Liu: Over-the-cell channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 408-418 (1990)
c21		Jason Cong, Bryan Preas, C. L. Liu: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715
c20		Jason Cong, C. L. Liu: On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463
c19		Xianjin Yao, C. L. Liu: Solution of a module orientation and rotation problem. EURO-DAC 1990: 584-588
c18		Nany Hasan, C. L. Liu: Fault covers in reconfigurable PLAs. FTCS 1990: 166-173
	1989
j16		D. F. Wong, C. L. Liu: Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989)
j15		Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal: Generalized latin squares I. Discrete Applied Mathematics 25(1-2): 155-178 (1989)
j14		Xianjin Yao, Masaaki Yamada, C. L. Liu: A new approach to the pin assignment problem. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 999-1006 (1989)
c17		Ran Libeskind-Hadas, C. L. Liu: Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. DAC 1989: 400-405
	1988
j13		Jason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)
c16		Xianji Yao, Masaaki Yamada, C. L. Liu: A New Approach to the Pin Assignment Problem. DAC 1988: 566-572
c15		Nany Hasan, C. L. Liu: Minimum fault coverage in reconfigurable arrays. FTCS 1988: 348-353
	1987
c14		D. F. Wong, C. L. Liu: Array Optimization for VLSI Synthesis. DAC 1987: 537-543
	1986
j12		J. L. Lewandowski, C. L. Liu, Jane W.-S. Liu: An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. J. Algorithms 7(3): 323-330 (1986)
c13		D. F. Wong, C. L. Liu: A new algorithm for floorplan design. DAC 1986: 101-107
	1985
j11		Prakash V. Ramanan, C. L. Liu: Permutation Representation of k-Ary Trees. Theor. Comput. Sci. 38: 83-98 (1985)
	1984
j10		Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu: A Personnel Assignment Problem. J. Algorithms 5(1): 132-144 (1984)
j9		J. R. Egan, C. L. Liu: Bipartite Folding and Partitioning of a PLA. IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 191-199 (1984)
	1983
j8		W.-D. Wei, C. L. Liu: On a Periodic Maintenance Problem. Oper. Res. Lett. 2(2): 90-93 (1983)
j7		D. T. Lee, C. L. Liu, C. K. Wong: (g 0, g 1, ... g k)-Trees and Unary OL Systems. Theor. Comput. Sci. 22: 209-217 (1983)
	1982
j6		C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman: Scheduling with Slack Time. Acta Inf. 17: 31-41 (1982)
c12		J. R. Egan, C. L. Liu: Optimal bipartite folding of PLA. DAC 1982: 141-146
	1980
c11		C. L. Liu: Generation of trees. CLAAP 1980: 45-53
	1978
j5		Jane W.-S. Liu, C. L. Liu: Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. Acta Inf. 10: 95-104 (1978)
	1976
c10		C. L. Liu: Deterministic Job Scheduling in Computing Systems. Performance 1976: 241-254
	1974
c9		Jane W.-S. Liu, C. L. Liu: Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. IFIP Congress 1974: 349-353
c8		N. F. Chen, C. L. Liu: On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. Sagamore Computer Conference 1974: 1-16
	1973
j4		C. L. Liu, James W. Layland: Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. J. ACM 20(1): 46-61 (1973)
c7		C. L. Liu: Analysis of sorting algorithms. AFIPS National Computer Conference 1973: 453
c6		C. K. Wong, C. L. Liu, J. Apter: A drum scheduling algorithm. Automatentheorie und Formale Sprachen 1973: 267-275
	1972
j3		C. L. Liu: Analysis and Synthesis of Sorting Algorithms. SIAM J. Comput. 1(4): 290-304 (1972)
c5		C. L. Liu: Optimal Scheduling on Multi-Processor Computing Systems. SWAT (FOCS) 1972: 155-160
	1971
c4		C. L. Liu: Analysis of Sorting Algorithms. SWAT (FOCS) 1971: 207-215
	1969
j2		C. L. Liu: A Note on Definite Stochastic Sequential Machines. Information and Control 14(4): 407-421 (1969)
j1		C. L. Liu: Lattice Functions, Pair Algebras, and Finite-State Machines. J. ACM 16(3): 442-454 (1969)
	1967
c3		C. L. Liu, G. D. Chang, R. E. Marks: The design and implementation of a table driven compiler system. AFIPS Spring Joint Computing Conference 1967: 691-697
	1966
c2		C. L. Liu: Pair Algebra and Its Application. SWAT (FOCS) 1966: 103-112
	1964
c1		C. L. Liu: Sequential-machine realization using feedback shift registers. SWCT (FOCS) 1964: 209-227

Coauthor Index

Colors in the list of coauthors

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