Chun-Yeh Liu

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	1995
c2		Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja: An optimized testable architecture for finite state machines. VTS 1995: 164-169
	1993
j1		Chun-Yeh Liu, Kewal K. Saluja: An efficient algorithm for bipartite PLA folding. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1839-1847 (1993)
	1987
c1		Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya: BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. DAC 1987: 385-391

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