Igor Loi

Christian Weis, Igor Loi, Luca Benini, Norbert Wehn: Exploration and Optimization of 3-D Integrated DRAM Subsystems. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 597-610 (2013)

Mohammad Reza Kakoee, Igor Loi, Luca Benini: A shared-FPU architecture for ultra-low power MPSoCs. Conf. Computing Frontiers 2013: 3

Mohammad Reza Kakoee, Igor Loi, Luca Benini: Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. IEEE Trans. on Circuits and Systems 59-II(12): 927-931 (2012)

Mohammad Reza Kakoee, Igor Loi, Luca Benini: A resilient architecture for low latency communication in shared-L1 processor clusters. DATE 2012: 887-892

Christian Weis, Igor Loi, Luca Benini, Norbert Wehn: An energy efficient DRAM subsystem for 3D integrated SoCs. DATE 2012: 1138-1141

Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini: 3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. VLSI-SoC 2012: 30-35

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal: Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. J. Solid-State Circuits 46(1): 293-307 (2011)

Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini: Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 124-134 (2011)

Christian Weis, Norbert Wehn, Igor Loi, Luca Benini: Design space exploration for 3D-stacked DRAMs. DATE 2011: 389-394

Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini: A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. DATE 2011: 491-496

Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini: Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. PATMOS 2011: 102-111

Igor Loi, Luca Benini: An efficient distributed memory interface for many-core platform with 3D stacked DRAM. DATE 2010: 99-104

Mohammad Reza Kakoee, Igor Loi, Luca Benini: A new physical routing approach for robust bundled signaling on NoC links. ACM Great Lakes Symposium on VLSI 2010: 3-8

Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini: 3D NoCs - Unifying inter & intra chip communication. ISCAS 2010: 3337-3340

Igor Loi, Federico Angiolini, Luca Benini: Synthesis of low-overhead configurable source routing tables for network interfaces. DATE 2009: 262-267

Igor Loi, Federico Angiolini, Luca Benini: Developing Mesochronous Synchronizers to Enable 3D NoCs. DATE 2008: 1414-1419

Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini: A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD 2008: 598-602

Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini: Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007 (2007)