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 | 2011 | |
|---|---|---|
| c11 |      | Libo Huang, Zhiying Wang, Li Shen, Hongyi Lu, Nong Xiao, Cong Liu: A specialized low-cost vectorized loop buffer for embedded processors. DATE 2011: 1200-1203 |
| 2010 | ||
| c10 | | Wei Shi, Zhiying Wang, Hongguang Ren, Ting Cao, Wei Chen, Bo Su, Hongyi Lu: DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time. ICCD 2010: 321-327 |
| 2009 | ||
| c9 | | Wei Chen, Zhiying Wang, Hongyi Lu, Li Shen, Nong Xiao, Zhong Zheng: A Hardware Approach for Reducing Interpretation Overhead. CIT (1) 2009: 98-103 |
| c8 | | Wei Chen, Li Shen, Hongyi Lu, Zhiying Wang, Nong Xiao: A Light-weight Code Cache Design for Dynamic Binary Translation. ICPADS 2009: 120-125 |
| c7 | | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao: Using Pcache to Speedup Interpretation in Dynamic Binary Translation. ISPA 2009: 525-530 |
| 2008 | ||
| c6 | | Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai: A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. DAC 2008: 630-633 |
| c5 | | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao: DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture. EUC (2) 2008: 399-404 |
| c4 | | Wei Chen, Hongyi Lu, Li Shen, Zhiying Wang, Nong Xiao, Dan Chen: A Novel Hardware Assisted Full Virtualization Technique. ICYCS 2008: 1292-1297 |
| 2006 | ||
| c3 | | Yuan-man Tong, Zhiying Wang, Kui Dai, Hongyi Lu: Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. Inscrypt 2006: 66-77 |
| c2 | | Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai: A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. VLSI-SoC 2006: 216-221 |
| 2004 | ||
| c1 | | Lei Wang, Hongyi Lu, Kui Dai, Zhiying Wang: TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC. Asia-Pacific Computer Systems Architecture Conference 2004: 126-136 |
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