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Shih-Lien Lu
2010 – today
- 2013
[c38]Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce Jacob: Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. HPCA 2013: 143-154- 2012
- [j17]Wei Wu, Dinesh Somasekhar, Shih-Lien Lu: Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. VLSI Syst. 20(11): 2147-2151 (2012)
- [c37]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky: Design for test and reliability in ultimate CMOS. DATE 2012: 677-682
- [c36]Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held: Scaling the "Memory Wall": Designer track. ICCAD 2012: 271-272
- [c35]Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi Iyer, Tong Li, Seung Eun Lee: Reducing L1 caches power by exploiting software semantics. ISLPED 2012: 391-396
- 2011
- [j16]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011)
- [j15]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De: A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. J. Solid-State Circuits 46(1): 194-208 (2011)
- [j14]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De: Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. J. Solid-State Circuits 46(4): 797-805 (2011)
- [j13]Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu: Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Trans. Computers 60(1): 50-63 (2011)
- [j12]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu: Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 441-454 (2011)
- [j11]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De: All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. on Circuits and Systems 58-I(9): 2017-2025 (2011)
- [c34]Ilya Wagner, Shih-Lien Lu: Distributed hardware matcher framework for SoC survivability. DATE 2011: 305-310
- [c33]Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu: Energy-efficient cache design using variable-strength error-correcting codes. ISCA 2011: 461-472
- [c32]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu: Integrating formal verification and high-level processor pipeline synthesis. SASP 2011: 22-29
- 2010
- [c31]James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De: Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625
- [c30]Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De: Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4
- [c29]Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam: Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC 2010: 314-319
- [c28]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu: Automatic pipelining from transactional datapath specifications. DATE 2010: 1001-1004
- [c27]Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu: Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA 2010: 83-93
- [c26]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356
- [c25]James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De: A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283
- [c24]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah: PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j10]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu: Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro 29(1): 96-103 (2009)
- [c23]Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien Lu: Content Addressable Memory for Low-Power and High-Performance Applications. CSIE (3) 2009: 423-427
- [c22]Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar: Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7
- [c21]James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik: Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD 2009: 71-73
- [c20]Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh: Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793
- [c19]Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu: Improving cache lifetime reliability at ultra-low voltages. MICRO 2009: 89-99
- 2008
- [j9]Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow: A Desktop Computer with a Reconfigurable Pentium®. TRETS 1(1) (2008)
- [j8]Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu: Active Cache Emulator. IEEE Trans. VLSI Syst. 16(3): 229-240 (2008)
- [c18]Changjian Gao, Shih-Lien Lu: Novel FPGA based Haar classifier face detection algorithm acceleration. FPL 2008: 373-378
- [c17]Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu: Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA 2008: 203-214
- [p1]Shih-Lien Lu, Ravichandran Ramachandran: Carry Logic. Wiley Encyclopedia of Computer Science and Engineering 2008
- 2007
- [j7]John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007)
- [c16]Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh: An FPGA-based Pentium in a complete desktop system. FPGA 2007: 53-59
- [c15]Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee: An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. FPL 2007: 47-53
- [c14]Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu: Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332
- [c13]Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy: Fine-Grained Redundancy in Adders. ISQED 2007: 317-321
- 2006
- [j6]Roger Morrison, Ben Lee, Shih-Lien Lu: Asymmetric Clustering using a Register Cache. J. Instruction-Level Parallelism 8 (2006)
- [c12]Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu: Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72
- 2005
- [c11]Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Pei-chun Chen: Improving branch prediction accuracy with parallel conservative correctors. Conf. Computing Frontiers 2005: 334-341
- [c10]Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu: Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS 2005: 12-20
- 2004
- [j5]
- [c9]Chunrong Lai, Shih-Lien Lu: Efficient Victim Mechanism on Sector Cache Organization. Asia-Pacific Computer Systems Architecture Conference 2004: 16-29
- 2003
- [c8]Shih-Lien Lu, Konrad Lai: Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL 2003: 638-647
- [c7]
- 2002
- [c6]
- [c5]Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai: Bloom filtering cache misses for accurate data speculation and prefetching. ICS 2002: 189-198
- [c4]Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai: Dynamic addressing memory arrays with physical locality. MICRO 2002: 161-170
- 2000
- [c3]
1990 – 1999
- 1998
- [c2]Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu: Non-Stalling CounterFlow Architecture. HPCA 1998: 334-341
- 1997
- [c1]Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller: Advances of the Counterflow Pipeline Microarchitecture. HPCA 1997: 230-236
- 1996
- [j4]Ravichandran Ramachandran, Shih-Lien Lu: Efficient arithmetic using self-timing. IEEE Trans. VLSI Syst. 4(4): 445-454 (1996)
- 1995
- [j3]Shih-Lien Lu: Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Trans. VLSI Syst. 3(2): 338-341 (1995)
- [j2]Chih-Ming Chang, Shih-Lien Lu: Design of a static MIMD data flow processor using micropipelines. IEEE Trans. VLSI Syst. 3(3): 370-378 (1995)
1980 – 1989
- 1988
- [j1]Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu: Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 998-1004 (1988)
Coauthor Index
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last updated on 2013-06-11 21:40 CEST by the dblp team