Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Wayne Luk
2010 – today
- 2013
[j76]Simon A. Spacey, Wayne Luk, Daniel Kuhn, Paul H. J. Kelly: Parallel partitioning for distributed systems using sequential assignment. J. Parallel Distrib. Comput. 73(2): 207-219 (2013)- [j75]Ka-Wai Kwok, Kuen Hung Tsoi, Valentina Vitiello, James Clark, Gary C. T. Chow, Wayne Luk, Guang-Zhong Yang: Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints. IEEE Transactions on Robotics 29(1): 15-31 (2013)
- [j74]David B. Thomas, Wayne Luk: The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. VLSI Syst. 21(4): 761-770 (2013)
- [c279]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski: Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12
- [c278]J. Arram, Kuen Hung Tsoi, Wayne Luk, P. Jiang: Hardware Acceleration of Genetic Sequence Alignment. ARC 2013: 13-24
- [c277]Maciej Kurek, Tobias Becker, Wayne Luk: Parametric Optimization of Reconfigurable Designs Using Machine Learning. ARC 2013: 134-145
- [c276]Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu: Automating resource optimisation in reconfigurable design (abstract only). FPGA 2013: 275
- 2012
- [j73]Ka Fai Cedric Yiu, Yao Lu, Chun Hok Ho, Wayne Luk, Jiaquan Huo, Sven Nordholm: Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device. Digital Signal Processing 22(2): 376-390 (2012)
- [j72]Simon A. Spacey, Wolfram Wiesemann, Daniel Kuhn, Wayne Luk: Robust Software Partitioning with Multiple Instantiation. INFORMS Journal on Computing 24(3): 500-515 (2012)
- [j71]Simon A. Spacey, Wayne Luk, Paul H. J. Kelly, Daniel Kuhn: Improving communication latency with the write-only architecture. J. Parallel Distrib. Comput. 72(12): 1617-1627 (2012)
- [j70]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung: Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Computer Architecture News 40(5): 10-15 (2012)
- [j69]Kuen Hung Tsoi, Tobias Becker, Wayne Luk: Modelling reconfigurable systems in event driven simulation. SIGARCH Computer Architecture News 40(5): 34-39 (2012)
- [j68]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides: Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers 61(12): 1800-1812 (2012)
- [j67]Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar: FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. VLSI Syst. 20(1): 52-65 (2012)
- [j66]Anson H. T. Tse, David B. Thomas, Wayne Luk: Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. VLSI Syst. 20(5): 818-826 (2012)
- [j65]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton: Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. VLSI Syst. 20(7): 1295-1303 (2012)
- [j64]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides: Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. Signal Processing Systems 67(1): 65-78 (2012)
- [c275]José Gabriel F. Coutinho, Tiago Carvalho, Sérgio Durand, João M. P. Cardoso, Ricardo Nobre, Pedro C. Diniz, Wayne Luk: Experiments with the LARA aspect-oriented approach. AOSD (Companion) 2012: 27-30
- [c274]João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Wayne Luk, Ricardo Nobre, Pedro C. Diniz, Zlatko Petrov: LARA: an aspect-oriented programming language for embedded systems. AOSD 2012: 179-190
- [c273]
- [c272]Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston: Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC 2012: 187-201
- [c271]Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk: Optimising Performance of Quadrature Methods with Reduced Precision. ARC 2012: 251-263
- [c270]Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk: Efficient Communication for FPGA Clusters. ARC 2012: 335-341
- [c269]Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk: A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP 2012: 8-15
- [c268]Tim Todman, Wayne Luk: Reconfigurable Design Automation by High-Level Exploration. ASAP 2012: 185-188
- [c267]Kyprianos Papadimitriou, Christian Pilato, Dionisios N. Pnevmatikatos, Marco D. Santambrogio, Catalin Bogdan Ciobanu, Tod Todman, Tobias Becker, Tom Davidson, Xinyu Niu, Georgi Gaydadjiev, Wayne Luk, Dirk Stroobandt: Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration. CSE 2012: 391-398
- [c266]José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov: Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE 2012: 399-406
- [c265]João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk: Controlling Hardware Synthesis with Aspects. DSD 2012: 226-233
- [c264]Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong: A Mixed Precision Methodology for Mathematical Optimisation. FCCM 2012: 33-36
- [c263]João M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk: Specifying Compiler Strategies for FPGA-based Systems. FCCM 2012: 192-199
- [c262]Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas: A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA 2012: 57-66
- [c261]
- [c260]Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk: Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL 2012: 99-104
- [c259]Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas: Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL 2012: 165-172
- [c258]Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell: Exploiting run-time reconfiguration in stencil computation. FPL 2012: 173-180
- [c257]Tim Todman, Wayne Luk: Verification of streaming designs by combining symbolic simulation and equivalence checking. FPL 2012: 203-208
- [c256]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski: Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530
- [c255]Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang: FPGA based memory efficient high resolution stereo vision system for video tolling. FPT 2012: 29-32
- [c254]Maciej Kurek, Wayne Luk: Parametric reconfigurable designs with Machine Learning Optimizer. FPT 2012: 109-112
- [c253]Tim Todman, Peter Boehm, Wayne Luk: Verification of streaming hardware and software codesigns. FPT 2012: 147-150
- [c252]Ce Guo, Haohuan Fu, Wayne Luk: A fully-pipelined expectation-maximization engine for Gaussian Mixture Models. FPT 2012: 182-189
- [c251]Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong: A partially reconfigurable architecture supporting hardware threads. FPT 2012: 269-276
- [c250]Kit Cheung, Simon R. Schultz, Wayne Luk: A Large-Scale Spiking Neural Network Accelerator for FPGA Systems. ICANN (1) 2012: 113-120
- [c249]Xinyu Niu, Kuen Hung Tsoi, Wayne Luk: Self-Adaptive Heterogeneous Cluster with Wireless Network. IPDPS Workshops 2012: 306-311
- [c248]Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura: Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig 2012: 1-7
- [c247]Marco D. Santambrogio, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Christian Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Donatella Sciuto: Smart technologies for effective reconfiguration: The FASTER approach. ReCoSoC 2012: 1-7
- 2011
- [j63]Kuen Hung Tsoi, Wayne Luk: Power profiling and optimization for heterogeneous multi-core systems. SIGARCH Computer Architecture News 39(4): 8-13 (2011)
- [j62]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes: A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. T. HiPEAC 4: 63-83 (2011)
- [j61]William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer: Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. T. HiPEAC 4: 354-369 (2011)
- [j60]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk: Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Transactions on Industrial Electronics 58(8): 3701-3716 (2011)
- [j59]Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert: Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Trans. VLSI Syst. 19(6): 1048-1061 (2011)
- [j58]Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. VLSI Syst. 19(12): 2229-2242 (2011)
- [c246]Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk: FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. ARC 2011: 181-192
- [c245]Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk: CusComNet: A customisable network for reconfigurable heterogeneous clusters. ASAP 2011: 9-16
- [c244]Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong: Mixed Precision Processing in Reconfigurable Systems. FCCM 2011: 17-24
- [c243]Qiwei Jin, Wayne Luk, David B. Thomas: On Comparing Financial Option Price Solvers on FPGA. FCCM 2011: 89-92
- [c242]Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk: A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). FPGA 2011: 281
- [c241]Qiwei Jin, Wayne Luk, David B. Thomas: Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL 2011: 6-9
- [c240]Xinyu Niu, Kuen Hung Tsoi, Wayne Luk: Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking. FPL 2011: 545-550
- [c239]Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj: A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT 2011: 1-8
- [c238]
- [c237]Adrien Le Masle, Gary Chun Tak Chow, Wayne Luk: Constant power reconfigurable computing. FPT 2011: 1-8
- [c236]Kong Woei Susanto, Wayne Luk: Automating formal verification of customized soft-processors. FPT 2011: 1-8
- [c235]Chi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung: Hydrate: Hybrid Reconfigurable Architecture Expressions. FPT 2011: 1-4
- [c234]Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston: Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing. ReConFig 2011: 176-181
- [c233]Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev: Power adaptive computing system design in energy harvesting environment. ICSAMOS 2011: 33-40
- [c232]Adrien Le Masle, Wayne Luk, Csaba Andras Moritz: Parametrized hardware architectures for the Lucas primality test. ICSAMOS 2011: 124-131
- 2010
- [j57]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfig. Comp. 2010 (2010)
- [j56]Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk: Multiloop Parallelisation Using Unrolling and Fission. Int. J. Reconfig. Comp. 2010 (2010)
- [j55]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined intra-chip signaling for on-FPGA communications. Integration 43(2): 188-201 (2010)
- [j54]Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti: HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. IEEE Micro 30(5): 88-97 (2010)
- [j53]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk: Efficient reconfigurable design for pricing asian options. SIGARCH Computer Architecture News 38(4): 14-20 (2010)
- [j52]Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, Wayne Luk: Programming framework for clusters with heterogeneous accelerators. SIGARCH Computer Architecture News 38(4): 53-59 (2010)
- [j51]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes: Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59(4): 433-448 (2010)
- [j50]Haohuan Fu, Oskar Mencer, Wayne Luk: FPGA Designs with Optimized Logarithmic Arithmetic. IEEE Trans. Computers 59(7): 1000-1006 (2010)
- [j49]Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen: Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010)
- [c231]Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver: Parametric Encryption Hardware Design. ARC 2010: 68-79
- [c230]Adrien Le Masle, Wayne Luk: Design space exploration of parametric pipelined designs. ASAP 2010: 47-54
- [c229]David B. Thomas, Wayne Luk: An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP 2010: 208-215
- [c228]Stephen Wray, Wayne Luk, Peter Pietzuch: Exploring algorithmic trading in reconfigurable hardware. ASAP 2010: 325-328
- [c227]Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung: Exploration of hardware sharing for image encoders. DATE 2010: 1737-1742
- [c226]Qiang Liu, Tim Todman, Wayne Luk: Combining optimizations in automated low power design. DATE 2010: 1791-1796
- [c225]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides: Customizable Composition and Parameterization of Hardware Design Transformations. DSD 2010: 595-602
- [c224]Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM 2010: 55-62
- [c223]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides: A Scripting Engine for Combining Design Transformations. FCCM 2010: 255-258
- [c222]
- [c221]David B. Thomas, Wayne Luk: FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL 2010: 77-82
- [c220]Stephen Wray, Wayne Luk, Peter Pietzuch: Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine. FPL 2010: 163-166
- [c219]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk: Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL 2010: 364-367
- [c218]Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong: A Karatsuba-Based Montgomery Multiplier. FPL 2010: 434-437
- [c217]Brahim Betkaoui, David B. Thomas, Wayne Luk: Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT 2010: 94-101
- [c216]Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk: Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT 2010: 233-240
- [c215]Vinay Sriram, David Cox, Kuen Hung Tsoi, Wayne Luk: Towards an embedded biologically-inspired machine vision processor. FPT 2010: 273-278
- [c214]Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk: Convex models for accelerating applications on FPGA-based clusters. FPT 2010: 495-498
- [c213]Tobias Becker, Markus Koester, Wayne Luk: Automated placement of reconfigurable regions for relocatable modules. ISCAS 2010: 3341-3344
2000 – 2009
- 2009
- [j48]Haohuan Fu, William G. Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk: Accelerating Seismic Computations Using Customized Number Representations on FPGAs. EURASIP J. Emb. Sys. 2009 (2009)
- [j47]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: High-throughput one-dimensional median and weighted median filters on FPGA. IET Computers & Digital Techniques 3(4): 384-394 (2009)
- [j46]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope: Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. TRETS 2(4) (2009)
- [j45]Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor: Hierarchical Segmentation for Hardware Function Evaluation. IEEE Trans. VLSI Syst. 17(1): 103-116 (2009)
- [j44]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Floating-Point FPGA: Architecture and Modeling. IEEE Trans. VLSI Syst. 17(12): 1709-1718 (2009)
- [c212]Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26
- [c211]Julien Lamoureux, Tony Field, Wayne Luk: Accelerating a Virtual Ecology Model with FPGAs. ASAP 2009: 67-74
- [c210]Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk: NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs. ASAP 2009: 137-144
- [c209]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128
- [c208]Philip G. Potter, Wayne Luk, Peter Y. K. Cheung: Partition-based exploration for reconfigurable JPEG designs. DATE 2009: 886-889
- [c207]Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann: Design optimizations to improve placeability of partial reconfiguration modules. DATE 2009: 976-981
- [c206]Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson: Harnessing Human Computation Cycles for the FPGA Placement Problem. ERSA 2009: 188-194
- [c205]Anson H. T. Tse, David B. Thomas, Wayne Luk: Accelerating Quadrature Methods for Option Valuation. FCCM 2009: 29-36
- [c204]David B. Thomas, Wayne Luk: FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM 2009: 45-52
- [c203]Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen: Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138
- [c202]David B. Thomas, Lee W. Howes, Wayne Luk: A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA 2009: 63-72
- [c201]Qiwei Jin, David B. Thomas, Wayne Luk: Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL 2009: 73-78
- [c200]Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: Modeling post-techmapping and post-clustering FPGA circuit depth. FPL 2009: 205-211
- [c199]Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides: Optimising designs by combining model-based and pattern-based transformations. FPL 2009: 308-313
- [c198]Gareth W. Morris, David B. Thomas, Wayne Luk: FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects 2009: 83-89
- [c197]Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William G. Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong: A high-level compilation toolchain for heterogeneous systems. SoCC 2009: 9-18
- [c196]Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee: Tuning instruction customisation for reconfigurable system-on-chip. SoCC 2009: 61-64
- [c195]Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk: Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation. SOFSEM 2009: 509-520
- 2008
- [j43]Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfig. Comp. 2008 (2008)
- [j42]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: Custom parallel caching schemes for hardware-accelerated image compression. J. Real-Time Image Processing 3(4): 289-302 (2008)
- [j41]Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor: Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations. IEEE Trans. Computers 57(5): 686-701 (2008)
- [j40]Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk: CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 528-541 (2008)
- [j39]
- [j38]Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk: A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. TRETS 1(1) (2008)
- [j37]David B. Thomas, Wayne Luk: Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. TRETS 1(2) (2008)
- [j36]Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown: Reconfigurable Architecture for Network Flow Analysis. IEEE Trans. VLSI Syst. 16(1): 57-65 (2008)
- [j35]Wayne Luk, Yvon Savaria, Oskar Mencer: Guest Editorial: 20 Years of ASAP. Signal Processing Systems 53(1-2): 1-2 (2008)
- [c194]Julien Lamoureux, Wayne Luk: An Overview of Low-Power Techniques for Field-Programmable Gate Arrays. AHS 2008: 338-345
- [c193]Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk: An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230
- [c192]Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope: Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC 2008: 243-253
- [c191]Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar: Fast custom instruction identification by convex subgraph enumeration. ASAP 2008: 1-6
- [c190]David B. Thomas, Wayne Luk: Resource efficient generators for the floating-point uniform and exponential distributions. ASAP 2008: 102-107
- [c189]Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk: Reconfigurable acceleration of microphone array algorithms for speech enhancement. ASAP 2008: 203-208
- [c188]Andreas Fidjeland, Wayne Luk, Stephen Muggleton: A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming. BCS Int. Acad. Conf. 2008: 318-330
- [c187]Ben Cope, Peter Y. K. Cheung, Wayne Luk: Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE 2008: 44-49
- [c186]William G. Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer: Power-Aware and Branch-Aware Word-Length Optimization. FCCM 2008: 129-138
- [c185]David B. Thomas, Wayne Luk: Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM 2008: 229-238
- [c184]David B. Thomas, Wayne Luk: FPGA-optimised high-quality uniform random number generators. FPGA 2008: 235-244
- [c183]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258
- [c182]Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226
- [c181]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232
- [c180]David B. Thomas, Wayne Luk: Sampling from the exponential distribution using independent Bernoulli variates. FPL 2008: 239-244
- [c179]Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong: Mapping and scheduling with task clustering for heterogeneous computing systems. FPL 2008: 275-280
- [c178]Markus Koester, Wayne Luk, Geoffrey Brown: A hardware compilation flow for instance-specific VLIW cores. FPL 2008: 619-622
- [c177]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694
- [c176]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16
- [c175]
- [c174]Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton: Optimizing coarse-grained units in floating point hybrid FPGA. FPT 2008: 57-64
- [c173]David B. Thomas, Wayne Luk: Estimation of sample mean and variance for Monte-Carlo simulations. FPT 2008: 89-96
- [c172]Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong: Unrolling-based loop mapping and scheduling. FPT 2008: 321-324
- [c171]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214
- [c170]Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk: Smart Enumeration: A Systematic Approach to Exhaustive Search. PATMOS 2008: 429-438
- [c169]Ben Cope, Peter Y. K. Cheung, Wayne Luk: Systematic design space exploration for customisable multi-processor architectures. ICSAMOS 2008: 57-64
- [c168]William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer: Reconfigurable design with clock gating. ICSAMOS 2008: 187-194
- [c167]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10
- [c166]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58
- 2007
- [j34]David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor: Gaussian random number generators. ACM Comput. Surv. 39(4) (2007)
- [j33]David B. Thomas, Wayne Luk: Non-uniform random number generation through piecewise linear approximations. IET Computers & Digital Techniques 1(4): 312-321 (2007)
- [j32]Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk: Real-time hardware acceleration of the trace transform. J. Real-Time Image Processing 2(4): 235-248 (2007)
- [j31]Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam: High-Performance Embedded Architecture and Compilation Roadmap. T. HiPEAC 1: 5-29 (2007)
- [j30]Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor: Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. IEEE Trans. VLSI Syst. 15(8): 952-962 (2007)
- [j29]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
- [j28]José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang: Designing a Posture Analysis System with Hardware Implementation. VLSI Signal Processing 47(1): 33-45 (2007)
- [j27]David B. Thomas, Wayne Luk: High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. VLSI Signal Processing 47(1): 77-92 (2007)
- [c165]David B. Thomas, Wayne Luk, Michael Stumpf: Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC 2007: 302-313
- [c164]David B. Thomas, Jacob A. Bower, Wayne Luk: Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. ASAP 2007: 168-173
- [c163]Ben Cope, Peter Y. K. Cheung, Wayne Luk: Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP 2007: 308-313
- [c162]Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar: Optimizing instruction-set extensible processors under data bandwidth constraints. DATE 2007: 588-593
- [c161]David B. Thomas, Wayne Luk: Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. FCCM 2007: 3-12
- [c160]Tobias Becker, Wayne Luk, Peter Y. K. Cheung: Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM 2007: 35-44
- [c159]
- [c158]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318
- [c157]Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton: A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41
- [c156]Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201
- [c155]William G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer: Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. FPL 2007: 617-620
- [c154]William G. Osborne, José Gabriel F. Coutinho, Ray C. C. Cheung, Wayne Luk, Oskar Mencer: Instrumented Multi-Stage Word-Length Optimization. FPT 2007: 89-96
- [c153]David B. Thomas, Wayne Luk: A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT 2007: 97-104
- [c152]
- [c151]Kentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto: FPGA-based Streaming Computation for Lattice Boltzmann Method. FPT 2007: 233-236
- [c150]Tim Todman, Haofan Fu, Oskar Mencer, Wayne Luk: Improving Bounds for FPGA Logic Minimization. FPT 2007: 245-248
- [c149]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182
- [c148]
- [i1]Tero Rissa, Adam Donlin, Wayne Luk: Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. CoRR abs/0710.4845 (2007)
- 2006
- [j26]Steve McKeever, Wayne Luk: Provably-correct hardware compilation tools based on pass separation techniques. Formal Asp. Comput. 18(2): 120-142 (2006)
- [j25]Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf: Dynamic clock-frequencies for FPGAs. Microprocessors and Microsystems 30(6): 388-397 (2006)
- [j24]Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong: A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. IEEE Trans. Computers 55(6): 659-671 (2006)
- [j23]Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides: Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1990-2000 (2006)
- [c147]Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216
- [c146]Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William G. Osborne: UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. ARC 2006: 389-400
- [c145]Arran Derbyshire, Tobias Becker, Wayne Luk: Incremental elaboration for run-time reconfigurable hardware designs. CASES 2006: 93-102
- [c144]Robert G. Dimond, Oskar Mencer, Wayne Luk: Automating processor customisation: optimised memory access and resource sharing. DATE 2006: 206-211
- [c143]Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk: Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. ERSA 2006: 184-190
- [c142]Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo: Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44
- [c141]David B. Thomas, Wayne Luk: Efficient Hardware Generation of Random Variates with Arbitrary Distributions. FCCM 2006: 57-66
- [c140]Robert G. Dimond, Oskar Mencer, Wayne Luk: Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. FCCM 2006: 175-184
- [c139]Oliver Pell, Wayne Luk: Generating Parametrised Hardware Libraries from Higher-Order Descriptions. FCCM 2006: 297-298
- [c138]Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk: Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6
- [c137]Andreas Fidjeland, Wayne Luk: Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. FPL 2006: 1-6
- [c136]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8
- [c135]Oliver Pell, Wayne Luk: Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. FPL 2006: 1-6
- [c134]David B. Thomas, Wayne Luk: Non-Uniform Random Number Generation Through Piecewise Linear Approximations. FPL 2006: 1-6
- [c133]Dong-U Lee, Ray C. C. Cheung, John D. Villasenor, Wayne Luk: Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. FPT 2006: 33-40
- [c132]Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk: An FPGA implementation of the simplex algorithm. FPT 2006: 49-56
- [c131]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336
- [c130]Haohuan Fu, Oskar Mencer, Wayne Luk: Comparing floating-point and logarithmic number representations for reconfigurable acceleration. FPT 2006: 337-340
- [c129]David B. Thomas, Jacob A. Bower, Wayne Luk: Hardware architectures for Monte-Carlo based financial simulations. FPT 2006: 377-380
- [c128]Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer: A Reconfigurable Simulation Framework for Financial Computation. ReConFig 2006: 30-38
- [c127]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176
- 2005
- [j22]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk: Optimizing Hardware Function Evaluation. IEEE Trans. Computers 54(12): 1520-1531 (2005)
- [j21]Tim Todman, José Gabriel F. Coutinho, Wayne Luk: Customisable Hardware Compilation. The Journal of Supercomputing 32(2): 119-137 (2005)
- [j20]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. VLSI Syst. 13(1): 39-57 (2005)
- [j19]Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong: A hardware Gaussian noise generator using the Wallace method. IEEE Trans. VLSI Syst. 13(8): 911-920 (2005)
- [j18]Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung: Customizable elliptic curve cryptosystems. IEEE Trans. VLSI Syst. 13(9): 1048-1059 (2005)
- [c126]Andreas Fidjeland, Wayne Luk: Customising Application-Speci.c Multiprocessor Systems: a Case Study. ASAP 2005: 239-246
- [c125]Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Automating custom-precision function evaluation for embedded processors. CASES 2005: 22-31
- [c124]
- [c123]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk: MiniBit: bit-width optimization via affine arithmetic. DAC 2005: 837-840
- [c122]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13
- [c121]Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung: Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE 2005: 24-29
- [c120]Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay: A Combined Hardware-Software Architecture for Network Flow. ERSA 2005: 149-155
- [c119]Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen: Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224
- [c118]Paul Baker, Tim Todman, Henry Styles, Wayne Luk: Reconfigurable Designs for Radiosity. FCCM 2005: 95-104
- [c117]José Gabriel F. Coutinho, Jun Jiang, Wayne Luk: Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. FCCM 2005: 245-254
- [c116]Robert G. Dimond, Oskar Mencer, Wayne Luk: CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. FPL 2005: 1-6
- [c115]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk: Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147
- [c114]Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk: Ziggurat-based Hardware Gaussian Random Number Generator. FPL 2005: 275-280
- [c113]Henry Styles, Wayne Luk: Compilation and Management of Phase-Optimized Reconfigurable Systems. FPL 2005: 311-316
- [c112]Sherif Yusuf, Wayne Luk: Bitwise Optimised CAM for Network Intrusion Detection Systems. FPL 2005: 444-449
- [c111]David B. Thomas, Wayne Luk: High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. FPT 2005: 61-68
- [c110]M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang: Custom Hardware Architectures for Posture Analysis. FPT 2005: 77-84
- [c109]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt: Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT 2005: 111-118
- [c108]Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180
- [c107]Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk: Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. FPT 2005: 215-222
- [c106]Andreas Fidjeland, Wayne Luk: An Overview of High-Level Synthesis of Multiprocessors for Logic Programming. FPT 2005: 333-334
- [c105]Oliver Pell, Wayne Luk: Quartz: a framework for correct and efficient reconfigurable design. ReConFig 2005
- [c104]David B. Thomas, Wayne Luk: High quality uniform random number generation for massively parallel simulations in FPGA. ReConFig 2005
- 2004
- [b1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis and optimization of DSP algorithms. Kluwer 2004, ISBN 978-1-4020-7930-6, pp. I-XI, 1-164
- [j17]Henry Styles, Wayne Luk: Exploiting Program Branch Probabilities in Hardware Compilation. IEEE Trans. Computers 53(11): 1408-1419 (2004)
- [j16]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers 53(12): 1523-1534 (2004)
- [j15]Oskar Mencer, Wayne Luk: Parameterized High Throughput Function Evaluation for FPGAs. VLSI Signal Processing 36(1): 17-25 (2004)
- [c103]W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk: Customisable EPIC Processor: Architecture and Tools. DATE 2004: 236-241
- [c102]Tero Rissa, Adam Donlin, Wayne Luk: Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. DATE 2004: 253-258
- [c101]Tim Todman, José Gabriel F. Coutinho, Wayne Luk: Customisable Hardware Compilation. ERSA 2004: 18-28
- [c100]Tero Rissa, Wayne Luk, Peter Y. K. Cheung: Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA 2004: 184-193
- [c99]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung: Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM 2004: 79-88
- [c98]Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones, Michael Smith, John D. Villasenor: A Flexible Hardware Encoder for Low-Density Parity-Check Codes. FCCM 2004: 101-111
- [c97]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272
- [c96]Tero Rissa, Peter Y. K. Cheung, Wayne Luk: SoftSONIC: A Customisable Modular Platform for Video Applications. FPL 2004: 54-63
- [c95]Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk: Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. FPL 2004: 364-373
- [c94]
- [c93]Steven J. E. Wilton, Su-Shin Ang, Wayne Luk: The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728
- [c92]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051
- [c91]
- [c90]
- [c89]Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk: Adaptive range reduction for hardware function evaluation. FPT 2004: 169-176
- [c88]Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung: A scalable hardware architecture for prime number validation. FPT 2004: 177-184
- [c87]Henry Styles, David B. Thomas, Wayne Luk: Pipelining designs with loop-carried dependencies. FPT 2004: 255-262
- [c86]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Scalable structured data access by combining autonomous memory blocks. FPT 2004: 457-460
- [c85]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Autonomous Memory Block for reconfigurable computing. ISCAS (2) 2004: 581-584
- [c84]
- [c83]Nicolas Telle, Wayne Luk, Ray C. C. Cheung: Customising Hardware Designs for Elliptic Curve Cryptography. SAMOS 2004: 274-283
- 2003
- [j14]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Wordlength optimization for linear digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1432-1442 (2003)
- [j13]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003)
- [c82]Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai: PyHDL: Hardware Scripting with Python. Engineering of Reconfigurable Systems and Algorithms 2003: 288-291
- [c81]T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay: Compiling Policy Descriptions into Reconfigurable Firewall Processors. FCCM 2003: 39-
- [c80]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM 2003: 69-
- [c79]Tim Todman, Wayne Luk: Real-time Extensions to a C-like Hardware Description Language. FCCM 2003: 302-304
- [c78]
- [c77]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL 2003: 396-405
- [c76]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615
- [c75]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Non-uniform Segmentation for Hardware Function Evaluation. FPL 2003: 796-807
- [c74]T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay: Irregular Reconfigurable CAM Structures for Firewall Applications. FPL 2003: 890-899
- [c73]Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai: Hardware Design with a Scripting Language. FPL 2003: 1040-1043
- [c72]Jun Jiang, Wayne Luk, Daniel Rueckert: FPGA-Based Computation of Free-Form Deformations. FPL 2003: 1057-1061
- [c71]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL 2003: 1071-1074
- [c70]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung: Hierarchical segmentation schemes for function evaluation. FPT 2003: 92-99
- [c69]T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung: High-level language extensions for run-time reconfigurable systems. FPT 2003: 144-151
- [c68]Andreas Fidjeland, Wayne Luk: Customising parallelism and caching for machine learning. FPT 2003: 204-211
- [c67]Jun Jiang, Wayne Luk, Daniel Rueckert: FPGA-based computation of free-form deformations in medical image registration. FPT 2003: 234-241
- [c66]Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk: Design space exploration with A Stream Compiler. FPT 2003: 270-277
- [c65]José Gabriel F. Coutinho, Wayne Luk: Source-directed transformations for hardware compilation. FPT 2003: 278-285
- [c64]Steve McKeever, Wayne Luk, Arran Derbyshire: Towards Verifying Parametrised Hardware Libraries with Relative Placement Information. HICSS 2003: 279
- [c63]
- [c62]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) 2003: 621-624
- 2002
- [j12]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Design Autom. for Emb. Sys. 6(4): 425-449 (2002)
- [c61]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM 2002: 3-12
- [c60]Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM 2002: 98-
- [c59]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum Wordlength Allocation. FCCM 2002: 219-228
- [c58]Henry Styles, Wayne Luk: Accelerating Radiosity Calculations Using Reconfigurable Platforms. FCCM 2002: 279-281
- [c57]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk: Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM 2002: 297-298
- [c56]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi: Customising Floating-Point Designs. FCCM 2002: 315-317
- [c55]Steve McKeever, Wayne Luk, Arran Derbyshire: Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries. FMCAD 2002: 342-359
- [c54]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang: Automating Customisation of Floating-Point Designs. FPL 2002: 523-533
- [c53]Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung: Run-Time Adaptive Flexible Instruction Processors. FPL 2002: 545-555
- [c52]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL 2002: 1148-1151
- [c51]
- [c50]José Gabriel F. Coutinho, Wayne Luk: Optimising and adapting high-level hardware designs. FPT 2002: 150-157
- [c49]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi: Floating-point bitwidth analysis via automatic differentiation. FPT 2002: 158-165
- [c48]Andreas Fidjeland, Wayne Luk, Stephen Muggleton: Scalable acceleration of inductive logic programs. FPT 2002: 252-259
- [c47]T. K. Lee, Sherif Yusuf, Wayne Luk, A. Sloman, Emil Lupu, Naranker Dulay: Development framework for firewall processors. FPT 2002: 352-355
- [c46]Jun Jiang, Wayne Luk, Daniel Rueckert: FPGA-based computation of free-form deformations. FPT 2002: 407-410
- [c45]Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung: Incremental programming for reconfigurable engines. FPT 2002: 411-415
- [c44]Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung: PD-XML: extensible markup language for processor description. FPT 2002: 437-440
- [c43]Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen: Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456
- 2001
- [j11]Shaori Guo, Wayne Luk: An integrated system for developing regular array designs. Journal of Systems Architecture 47(3-4): 315-337 (2001)
- [j10]Markus Weinhardt, Wayne Luk: Pipeline vectorization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 234-248 (2001)
- [j9]Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo: Quantitative Analysis of FPGA-based Database Searching. VLSI Signal Processing 28(1-2): 85-96 (2001)
- [c42]Steve McKeever, Wayne Luk: Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques. CHARME 2001: 212-227
- [c41]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797
- [c40]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: The Multiple Wordlength Paradigm. FCCM 2001: 51-60
- [c39]Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk: The Effect of FPGA Granularity on Video Codec Implementations. FCCM 2001: 287-288
- [c38]
- [c37]Nicolas Boullis, Oskar Mencer, Wayne Luk, Henry Styles: Pipelined Function Evaluation on FPGAs. FCCM 2001: 304-306
- [c36]
- [c35]Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles: Parameterized Function Evaluation for FPGAs. FPL 2001: 544-554
- [c34]Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk: A Digit-Serial Structure for Reconfigurable Multipliers. FPL 2001: 565-573
- 2000
- [j8]Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk: Video Image Processing with the Sonic Architecture. IEEE Computer 33(4): 50-57 (2000)
- [j7]Jeffrey Arnold, Wayne Luk, Ken Pocek: Guest Editors' Introduction. VLSI Signal Processing 24(2-3): 127 (2000)
- [c33]
- [c32]Henry Styles, Wayne Luk: Customizing Graphics Applications: Techniques and Programming Interface. FCCM 2000: 77-90
- [c31]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple Precision for Resource Minimization. FCCM 2000: 307-308
- [c30]
- [c29]Arran Derbyshire, Wayne Luk: Combining Serialization and Reconfiguration for Convolver Designs. FCCM 2000: 344-346
- [c28]Jörn Gause, Peter Y. K. Cheung, Wayne Luk: Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL 2000: 96-105
- [c27]Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk: A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. FPL 2000: 361-370
- [c26]Arran Derbyshire, Wayne Luk: Combining Serialisation and Reconfiguration for FPGA Designs. FPL 2000: 636-645
- [c25]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple-Wordlength Resource Binding. FPL 2000: 646-655
1990 – 1999
- 1999
- [c24]
- [c23]Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung: Reconfigurable Computing for Augmented Reality. FCCM 1999: 136-145
- [c22]Dan Benyamin, John D. Villasenor, Wayne Luk: Optimizing FPGA-Based Vector Product Designs. FCCM 1999: 188-