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 | 2013 | |
|---|---|---|
| j16 |      | Jingqing Mu, Karthik Shankar, Roman L. Lysecky: Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems. ACM Trans. Embedded Comput. Syst. 12(3): 85 (2013) |
| 2012 | ||
| j15 | | Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda: A self-tuning design methodology for power-efficient multi-core systems. ACM Trans. Design Autom. Electr. Syst. 18(1): 4 (2012) |
| c28 | | Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky: Online algorithms for wireless sensor networks dynamic optimization. CCNC 2012: 180-187 |
| c27 | | Jingqing Mu, Roman L. Lysecky: Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems. CODES+ISSS 2012: 265-274 |
| 2011 | ||
| j14 | | Ajay Nair, Karthik Shankar, Roman L. Lysecky: Efficient hardware-based nonintrusive dynamic application profiling. ACM Trans. Embedded Comput. Syst. 10(3): 32 (2011) |
| c26 | | Jingqing Mu, Roman L. Lysecky: Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems. ASP-DAC 2011: 737-742 |
| 2010 | ||
| j13 | | Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross: Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks. Embedded Systems Letters 2(1): 10-13 (2010) |
| j12 | | Karthik Shankar, Roman L. Lysecky: Control Focused Soft Error Detection for Embedded Applications. Embedded Systems Letters 2(4): 127-130 (2010) |
| j11 | | Rahul Kalra, Roman L. Lysecky: Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems. IEEE Trans. VLSI Syst. 18(4): 671-674 (2010) |
| c25 | | Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang: Workload capacity considering NBTI degradation in multi-core systems. ASP-DAC 2010: 450-455 |
| c24 | | Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda: A self-evolving design methodology for power efficient multi-core systems. ICCAD 2010: 264-268 |
| c23 | | Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross: Transaction-Level Modeling for Sensor Networks Using SystemC. SUTC/UMC 2010: 197-204 |
| c22 | | Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky: A lightweight dynamic optimization methodology for wireless sensor networks. WiMob 2010: 129-136 |
| 2009 | ||
| j10 | | Lance Saldanha, Roman L. Lysecky: Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors. Design Autom. for Emb. Sys. 13(3): 139-157 (2009) |
| j9 | | Roman L. Lysecky, Frank Vahid: Design and implementation of a MicroBlaze-based warp processor. ACM Trans. Embedded Comput. Syst. 8(3) (2009) |
| j8 | | Jingqing Mu, Roman L. Lysecky: Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009) |
| c21 | | Karthik Shankar, Roman L. Lysecky: Non-intrusive dynamic application profiling for multitasked applications. DAC 2009: 130-135 |
| 2008 | ||
| j7 | | Frank Vahid, Greg Stitt, Roman L. Lysecky: Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. IEEE Computer 41(7): 40-46 (2008) |
| j6 | | Roman L. Lysecky: Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning. International Journal of Parallel Programming 36(5): 478-492 (2008) |
| c20 | | Ajay Nair, Roman L. Lysecky: Non-intrusive dynamic application profiler for detailed loop execution characterization. CASES 2008: 23-30 |
| c19 | | Lance Saldanha, Roman L. Lysecky: Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. CODES+ISSS 2008: 49-54 |
| c18 | | Mark Hammerquist, Roman L. Lysecky: Design space exploration for application specific FPGAS in system-on-a-chip designs. SoCC 2008: 279-282 |
| 2007 | ||
| c17 | | Roman L. Lysecky: Low-power warp processor for power efficient high-performance embedded systems. DATE 2007: 141-146 |
| i1 | | Roman L. Lysecky, Frank Vahid: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. CoRR abs/0710.4705 (2007) |
| 2006 | ||
| j5 | | Roman L. Lysecky, Greg Stitt, Frank Vahid: Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006) |
| c16 | | David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen: Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268 |
| c15 | | David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky: Conjoining soft-core FPGA processors. ICCAD 2006: 694-701 |
| 2005 | ||
| c14 | | Roman L. Lysecky, Frank Vahid: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. DATE 2005: 18-23 |
| c13 | | Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62 |
| c12 | | Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers: Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). FPGA 2005: 271 |
| 2004 | ||
| j4 | | Chuanjun Zhang, Frank Vahid, Roman L. Lysecky: A self-tuning cache architecture for embedded systems. ACM Trans. Embedded Comput. Syst. 3(2): 407-425 (2004) |
| j3 |  | Roman L. Lysecky, Susan Cotterell, Frank Vahid: A fast on-chip profiler memory using a pipelined binary tree. IEEE Trans. VLSI Syst. 12(1): 120-122 (2004) |
| c11 | | Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959 |
| c10 | | Chuanjun Zhang, Frank Vahid, Roman L. Lysecky: A Self-Tuning Cache Architecture for Embedded Systems. DATE 2004: 142-147 |
| c9 | | Roman L. Lysecky, Frank Vahid: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. DATE 2004: 480-485 |
| 2003 | ||
| j2 | | Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt: Highly configurable platforms for embedded computing systems. Microelectronics Journal 34(11): 1025-1029 (2003) |
| c8 | | |
| c7 | | Greg Stitt, Roman L. Lysecky, Frank Vahid: Dynamic hardware/software partitioning: a first approach. DAC 2003: 250-255 |
| c6 | | |
| 2002 | ||
| j1 | | Roman L. Lysecky, Frank Vahid: Prefetching for improved bus wrapper performance in cores. ACM Trans. Design Autom. Electr. Syst. 7(1): 58-90 (2002) |
| c5 | | |
| 2000 | ||
| c4 | | Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky: A first-step towards an architecture tuning methodology for low power. CASES 2000: 187-192 |
| c3 | | Roman L. Lysecky, Frank Vahid, Tony Givargis: Techniques for Reducing Read Latency of Core Bus Wrappers. DATE 2000: 84-91 |
| c2 | | Roman L. Lysecky, Frank Vahid, Tony Givargis: Experiments with the Peripheral Virtual Component Interface. ISSS 2000: 221-224 |
| 1999 | ||
| c1 | | Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis: Pre-Fetching for Improved Core Interfacing. ISSS 1999: 51-55 |
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