Terrence S. T. Mak

Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon: On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. IEEE Trans. Biomed. Engineering 60(1): 198-202 (2013)

Terrence S. T. Mak: Truncation error analysis of MTBF computation for multi-latch synchronizers. Microelectronics Journal 43(2): 160-163 (2012)

Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi: Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distrib. Syst. 23(7): 1205-1215 (2012)

Andrew Mundy, Terrence S. T. Mak, Alex Yakovlev, Simon Davidson, Steve Furber: Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication. ACSD 2012: 62-71

Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev: Minimizing power supply noise through harmonic mappings in networks-on-chip. CODES+ISSS 2012: 113-122

Graeme Coapes, Terrence S. T. Mak, Junwen Luo, Alex Yakovlev, Chi-Sang Poon: A scalable FPGA-based design for field programmable large-scale ion channel simulations. FPL 2012: 112-119

Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev: Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. FPL 2012: 373-379

Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk: Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Transactions on Industrial Electronics 58(8): 3701-3716 (2011)

Yu Zhou, Terrence S. T. Mak, Alex Yakovlev: Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems. ACSD 2011: 67-76

Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi: Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502

Yu Li, Terrence S. T. Mak, Alex Yakovlev: Redressing timing issues for speed-independent circuits in deep submicron age. DATE 2011: 1376-1381

Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev: Power adaptive computing system design in energy harvesting environment. ICSAMOS 2011: 33-40

Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon: On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS 2011: 318-325

Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon: Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. VLSI-SoC 2011: 98-101

Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev: Communication centric on-chip power grid models for networks-on-chip. VLSI-SoC 2011: 180-183

Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon: Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. VLSI-SoC 2011: 354-358

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined intra-chip signaling for on-FPGA communications. Integration 43(2): 188-201 (2010)

Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon: A CMOS Current-Mode Dynamic Programming Circuit. IEEE Trans. on Circuits and Systems 57-I(12): 3112-3123 (2010)

Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon: A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. FPL 2010: 556-561

Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128

Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung: Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16

Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10

Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58

Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon: A Current-Mode Analog Circuit for Reinforcement Learning Problems. ISCAS 2007: 1301-1304

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182

Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8

Terrence S. T. Mak, Kai-Pui Lam: Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. CSB 2004: 512-514

Terrence S. T. Mak, Kai-Pui Lam: FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. FPL 2004: 1076-1079

Terrence S. T. Mak, Kai-Pui Lam: On Computing Maximum Likelihood Phylogeny Using FPGA p. FPL 2004: 1188

Terrence S. T. Mak, Kai-Pui Lam: High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. CSB 2003: 470-473