Yiorgos Makris

Ke Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris: Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests. DATE 2013: 553-558

Michail Maniatakos, Maria K. Michael, Yiorgos Makris: AVF-driven parity optimization for MBU protection of in-core memory arrays. DATE 2013: 1480-1485

Nathan Kupp, Yiorgos Makris: Applying the Model-View-Controller Paradigm to Adaptive Test. IEEE Design & Test of Computers 29(1): 28-35 (2012)

Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris: Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. IEEE Trans. Computers 61(10): 1361-1370 (2012)

Eric Love, Yier Jin, Yiorgos Makris: Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition. IEEE Transactions on Information Forensics and Security 7(1): 25-40 (2012)

Yier Jin, Dzmitry Maliuk, Yiorgos Makris: Post-deployment trust evaluation in wireless cryptographic ICs. DATE 2012: 965-970

Ke Huang, John M. Carulli Jr., Yiorgos Makris: Parametric counterfeit IC detection via Support Vector Machines. DFT 2012: 7-12

Nathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris: Spatial correlation modeling for probe test cost reduction in RF devices. ICCAD 2012: 23-29

Yier Jin, Michail Maniatakos, Yiorgos Makris: Exposing vulnerabilities of untrusted computing platforms. ICCD 2012: 131-134

Dzmitry Maliuk, Yiorgos Makris: A dual-mode weight storage analog neural network platform for on-chip applications. ISCAS 2012: 2889-2892

Nathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris: Spatial estimation of wafer measurement parameters using Gaussian process models. ITC 2012: 1-8

Nathan Kupp, Yiorgos Makris: Integrated optimization of semiconductor manufacturing: A machine learning approach. ITC 2012: 1-10

Michail Maniatakos, Maria K. Michael, Yiorgos Makris: Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors. ITC 2012: 1-8

Dzmitry Maliuk, Nathan Kupp, Yiorgos Makris: Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier. VTS 2012: 62-67

Yier Jin, Yiorgos Makris: Proof carrying-based information flow tracking for data secrecy protection and hardware trust. VTS 2012: 252-257

Nathan Kupp, He Huang, Yiorgos Makris, Petros Drineas: Improving Analog and RF Device Yield through Performance Calibration. IEEE Design & Test of Computers 28(3): 64-75 (2011)

Alfredo Benso, Yiorgos Makris, Pinaki Mazumder: Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications. IEEE Trans. Computers 60(4): 450-451 (2011)

Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. IEEE Trans. Computers 60(9): 1260-1273 (2011)

Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris: Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. IEEE Trans. Computers 60(9): 1274-1287 (2011)

Nathan Kupp, Mustapha Slamani, Yiorgos Makris: Correlating inline data with final test outcomes in analog/RF devices. DATE 2011: 812-817

Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: AVF Analysis Acceleration via Hierarchical Fault Pruning. European Test Symposium 2011: 87-92

Eric Love, Yier Jin, Yiorgos Makris: Enhancing security via provably trustworthy hardware intellectual property. HOST 2011: 12-17

Nathan Kupp, Haralampos-G. D. Stratigopoulos, Petros Drineas, Yiorgos Makris: On proving the efficiency of alternative RF tests. ICCAD 2011: 762-767

Yier Jin, Yiorgos Makris: Is single-scheme Trojan prevention sufficient? ICCD 2011: 305-308

Yier Jin, Yiorgos Makris: PSCML: Pseudo-Static Current Mode Logic. ICECS 2011: 41-44

Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer: Exponent monitoring for low-cost concurrent error detection in FPU control logic. VTS 2011: 235-240

Yier Jin, Yiorgos Makris: Hardware Trojans in Wireless Cryptographic ICs. IEEE Design & Test of Computers 27(1): 26-35 (2010)

Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris: RF Specification Test Compaction Using Learning Machines. IEEE Trans. VLSI Syst. 18(6): 998-1002 (2010)

Yier Jin, Nathan Kupp, Yiorgos Makris: DFTT: Design for Trojan Test. ICECS 2010: 1168-1171

Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, Yiorgos Makris: An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits. IOLTS 2010: 71-76

Nathan Kupp, He Huang, Petros Drineas, Yiorgos Makris: Post-production performance calibration in analog/RF devices. ITC 2010: 245-254

Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris: Analog neural network design for RF built-in self-test. ITC 2010: 684-693

Michail Maniatakos, Yiorgos Makris: Workload-driven selective hardening of control state elements in modern microprocessors. VTS 2010: 159-164

Nathan Kupp, Petros Drineas, Mustapha Slamani, Yiorgos Makris: On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction. J. Electronic Testing 25(6): 309-321 (2009)

Feng Shi, Yiorgos Makris: Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits. IEEE Trans. Computers 58(3): 394-408 (2009)

Sobeeh Almukhaizim, Feng Shi, Eric Love, Yiorgos Makris: Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits. IEEE Trans. VLSI Syst. 17(7): 869-882 (2009)

Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris: Enrichment of limited training sets in machine-learning-based analog/RF test. DATE 2009: 1668-1673

Yiorgos Makris: Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors. DFT 2009: 421-421

Yier Jin, Nathan Kupp, Yiorgos Makris: Experiences in Hardware Trojan Design and Implementation. HOST 2009: 50-57

Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Impact analysis of performance faults in modern microprocessors. ICCD 2009: 91-96

Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris: Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. VTS 2009: 9-14

Yiorgos Makris, Haralampos-G. D. Stratigopoulos: Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest. VTS 2009: 233

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 339-351 (2008)

Sobeeh Almukhaizim, Yiorgos Makris: Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires. IEEE Transactions on Reliability 57(1): 23-31 (2008)

Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti: Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. DFT 2008: 454-462

Nathan Kupp, Petros Drineas, Mustapha Slamani, Yiorgos Makris: Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction. European Test Symposium 2008: 35-40

Yier Jin, Yiorgos Makris: Hardware Trojan Detection Using Path Delay Fingerprint. HOST 2008: 51-57

Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris: On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS 2008: 123-128

Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Yiorgos Makris: On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. ITC 2008: 1-10

James Dardig, Haralampos-G. D. Stratigopoulos, Eric Stern, Mark Reed, Yiorgos Makris: A Statistical Approach to Characterizing and Testing Functionalized Nanowires. VTS 2008: 267-274

Yiorgos Makris, Alex Orailoglu: On the identification of modular test requirements for low cost hierarchical test path construction. Integration 40(3): 315-325 (2007)

Sobeeh Almukhaizim, Yiorgos Makris: Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines. IEEE Trans. Computers 56(6): 785-798 (2007)

Haralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris: Non-RF to RF Test Correlation Using Learning Machines: A Case Study. VTS 2007: 9-14

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Concurrent detection of erroneous responses in linear analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 878-891 (2006)

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1547-1554 (2006)

Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Yiorgos Makris: Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. ASYNC 2006: 46-56

Feng Shi, Yiorgos Makris: A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. ASYNC 2006: 57-67

Sobeeh Almukhaizim, Yiorgos Makris: Berger code-based concurrent error detection in asynchronous burst-mode machines. DATE 2006: 71-72

Feng Shi, Yiorgos Makris: Testing delay faults in asynchronous handshake circuits. ICCAD 2006: 193-197

Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris: Seamless Integration of SER in Rewiring-Based Design Space Exploration. ITC 2006: 1-9

Andreas G. Veneris, Yiorgos Makris: Session Abstract. VTS 2006: 290-291

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. VTS 2006: 406-411

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: Compaction-based concurrent error detection for digital circuits. Microelectronics Journal 36(9): 856-862 (2005)

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Nonlinear decision boundaries for testing analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1760-1773 (2005)

Feng Shi, Yiorgos Makris: SPIN-PAC: test compaction for speed-independent circuits. ASP-DAC 2005: 71-74

Sobeeh Almukhaizim, Yiorgos Makris: Concurrent Error Detection in Asynchronous Burst-Mode Controllers. DATE 2005: 1272-1277

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Generating decision regions in analog measurement spaces. ACM Great Lakes Symposium on VLSI 2005: 88-91

Feng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh: Test generation for ultra-high-speed asynchronous pipelines. ITC 2005: 10

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Constructive Derivation of Analog Specification Test Criteria. VTS 2005: 395-400

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: An Analog Checker with Input-Relative Tolerance for Duplicate Signals. J. Electronic Testing 20(5): 479-488 (2004)

Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu: Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. IEEE Transactions on Reliability 53(2): 269-278 (2004)

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: On Concurrent Error Detection with Bounded Latency in FSMs. DATE 2004: 596-603

Feng Shi, Yiorgos Makris: Fault simulation and random test generation for speed-independent circuits. ACM Great Lakes Symposium on VLSI 2004: 127-130

Feng Shi, Yiorgos Makris: SPIN-TEST: automatic test pattern generation for speed-independent circuits. ICCAD 2004: 903-908

Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorgos Makris: Compiler-Based Frame Formation for Static Optimization. ICCD 2004: 466-471

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction. ISQED 2004: 459-464

Feng Shi, Yiorgos Makris: SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. ITC 2004: 597-606

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: Cost-Driven Selection of Parity Trees. VTS 2004: 319-324

Petros Drineas, Yiorgos Makris: SPaRe: selective partial replication for concurrent fault-detection in FSMs. IEEE T. Instrumentation and Measurement 52(6): 1729-1737 (2003)

Petros Drineas, Yiorgos Makris: Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees. DATE 2003: 11164-11167

Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos: Low Cost Convolutional Code Based Concurrent Error Detection in FSMs. DFT 2003: 344-351

Sobeeh Almukhaizim, Yiorgos Makris: Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code. DFT 2003: 563-570

Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris: Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. ICCD 2003: 194-197

Petros Drineas, Yiorgos Makris: Independent Test Sequence Compaction through Integer Programming. ICCD 2003: 380-386

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: An Analog Checker With Input-Relative Tolerance for Duplicate Signals. IOLTS 2003: 54-

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris: On Compaction-Based Concurrent Error Detection. IOLTS 2003: 157

Petros Drineas, Yiorgos Makris: Concurrent Fault Detection in Random Combinational Logic. ISQED 2003: 425-430

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: Concurrent Error Detection in Linear Analog Circuits Using State Estimation. ITC 2003: 1164-1173

Petros Drineas, Yiorgos Makris: SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs. VLSI Design 2003: 167-

Haralampos-G. D. Stratigopoulos, Yiorgos Makris: An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. VTS 2003: 209-218

Yiorgos Makris, Jamison Collins, Alex Orailoglu: Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. J. Electronic Testing 18(1): 29-42 (2002)

Petros Drineas, Yiorgos Makris: Non-Intrusive Design of Concurrently Self-Testable FSMs. Asian Test Symposium 2002: 33-

Yiorgos Makris, Alex Orailoglu: Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. Asian Test Symposium 2002: 134-139

Thomas Verdel, Yiorgos Makris: Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. DFT 2002: 345-353

Yiorgos Makris, Vishal Patel, Alex Orailoglu: Efficient Transparency Extraction and Utilization in Hierarchical Test. VTS 2001: 246-251

Yiorgos Makris, Jamison Collins, Alex Orailoglu: Fast hierarchical test path construction for DFT-free controller-datapath circuits. Asian Test Symposium 2000: 185-190

Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu: Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. VTS 2000: 459-464

Yiorgos Makris, Alex Orailoglu: Channel-Based Behavioral Test Synthesis for Improved Module Reachability. DATE 1999: 283-288

Yiorgos Makris, Alex Orailoglu: A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. DFT 1999: 339-347

Yiorgos Makris, Alex Orailoglu: RTL Test Justification and Propagation Analysis for Modular Designs. J. Electronic Testing 13(2): 105-120 (1998)

Yiorgos Makris, Alex Orailoglu: DFT guidance through RTL test justification and propagation analysis. ITC 1998: 668-677