Wojciech Maly

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly: Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD 2013: 130-136

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly: Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED 2012: 384-390

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly: On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 229-241 (2011)

Wojciech Maly: Vertical slit transistor based integrated circuits (veSTICs): feasibility study. ISPD 2011: 147-148

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly: Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 197-210 (2010)

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly: Performance study of VeSFET-based, high-density regular circuits. ISPD 2010: 161-168

Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly: Evaluating yield and testing impact of sub-wavelength lithography. VTS 2010: 200-205

Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel: Adder Circuits with Transistors using Independently Controlled Gates. ISCAS 2009: 449-452

Wojciech Maly: Vertical slit transistor based integrated circuits (VeSTICs) paradigm. ISPD 2009: 63-64

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly: Transistor-level layout of high-density regular circuits. ISPD 2009: 83-90

Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey: More Moore: foolish, feasible, or fundamentally different? ICCAD 2008: 9

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz: Is there always performance overhead for regular fabric? ICCD 2008: 557-562

Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska: OPC-Free and Minimally Irregular IC Design Style. DAC 2007: 954-957

Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer: Extracting Defect Density and Size Distributions from Product ICs. IEEE Design & Test of Computers 23(5): 390-400 (2006)

Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton: Extraction of defect density and size distributions from wafer sort test results. DATE 2006: 913-918

Yangdong Steve Deng, Wojciech Maly: 2.5D system integration: a design driven system implementation schema. ASP-DAC 2004: 450-455

Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary: Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC 2004: 508-517

Yangdong Deng, Wojciech Maly: Physical Design of the "2.5D" Stacked System. ICCD 2003: 211-217

Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton: Progressive Bridge Identification. ITC 2003: 309-318

Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey: Deformations of IC Structure in Test and Yield Learning. ITC 2003: 856-865

Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly: Modeling the Economics of Testing: A DFT Perspective. IEEE Design & Test of Computers 19(1): 29-41 (2002)

Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels: Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC 2002: 233-241

Wojciech Maly: IC Design in High-Cost Nanometer-Technologies Era. DAC 2001: 9-14

Yangdong Deng, Wojciech Maly: Interconnect characteristics of 2.5-D system integration scheme. ISPD 2001: 171-175

Wojciech Maly: Quality of Design from an IC Manufacturing Perspective. ISQED 2001: 235-236

John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly: Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267

John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare: Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298

Peng Li, Pranab K. Nag, Wojciech Maly: Cost based tradeoff analysis of standard cell designs. SLIP 2000: 129-135

Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly: A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 151-162 (1999)

Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas: An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 494-501 (1999)

Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare: Design-Manufacturing Interface: Part I - Vision. DATE 1998: 550-556

Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon: Design-Manufacturing Interface: Part II - Applications. DATE 1998: 557-562

Hans T. Heineken, Wojciech Maly: Performance - Manufacturability Tradeoffs in IC Design. DATE 1998: 563-567

Wojciech Maly: Moore's law and physical design of ICs. ISPD 1998: 36

Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas: A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD 1998: 129-134

Anne E. Gattiker, Wojciech Maly: Toward understanding "Iddq-only" fails. ITC 1998: 174-183

Anne E. Gattiker, Wojciech Maly: Smart Substrate MCMs. J. Electronic Testing 10(1-2): 39-53 (1997)

Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly: Behavior and testability preservation under the retiming transformation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 528-543 (1997)

Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz: CAD at the Design-Manufacturing Interface. DAC 1997: 321-326

Witold A. Pleskacz, Wojciech Maly: Improved Yield Model for Submicron Domain. DFT 1997: 2-10

Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken: Detection of Yield Trends. DFT 1997: 62-68

Anne E. Gattiker, Wojciech Maly: Current Signatures: Application. ITC 1997: 156-165

Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly: To DFT or Not to DFT? ITC 1997: 557-566

Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly: So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC 1997: 1037-1038

Anne E. Gattiker, Wojciech Maly: Current signatures: application [to CMOS]. ITC 1997: 1168-1177

Wojciech Maly: The future of IC design, testing, and manufacturing. IEEE Design & Test of Computers 13(4): 8, 89-91 (1996)

Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski: A complexity analysis of sequential ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1409-1423 (1996)

Hans T. Heineken, Wojciech Maly: Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ICCAD 1996: 368-373

Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag: Design for manufacturability in submicron domain. ICCAD 1996: 690-697

Thomas E. Marchok, Wojciech Maly: Modeling the Difficulty of Sequential Automatic Test Pattern Generation. ICCD 1996: 261-

Wojciech Maly: New and Not-So-New Test Challenges of the Next Decade. ITC 1996: 11

Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly: I_DDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792

Anne E. Gattiker, Wojciech Maly: Current signatures [VLSI circuit testing]. VTS 1996: 112-117

Jitendra Khare, Wojciech Maly, Nathan Tiday: Fault characterization of standard cell libraries using inductive contamination. VTS 1996: 405-413

Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly: Testability Implications of Performance-Driven Logic Synthesis. IEEE Design & Test of Computers 12(2): 32-39 (1995)

Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly: On Test Set Preservation of Retimed Circuits. DAC 1995: 176-182

Jitendra Khare, Wojciech Maly: Inductive Contamination Analysis (ICA) with SRAM Application. ITC 1995: 552-560

Wojciech Maly, Derek Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas: Smart-Substrate Multichip-Module Systems. IEEE Design & Test of Computers 11(2): 64-73 (1994)

Wojciech Maly: Cost of Silicon Viewed from VLSI Design Perspective. DAC 1994: 135-142

Anne E. Gattiker, Wojciech Maly: Feasibility Study of Smart Substrate Multichip Modules. ITC 1994: 41-49

Wojciech Maly: Integration of Design, Manufacturing and Testing. ITC 1994: 1017

Samir Naik, Frank Agricola, Wojciech Maly: Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. IEEE Design & Test of Computers 10(2): 13-23 (1993)

Wojciech Maly: Prospects for WSI: A Manufacturing Perspective. IEEE Computer 25(4): 58-65 (1992)

Wojciech Maly, Marek J. Patyra: Design of ICs applying built-in current testing. J. Electronic Testing 3(4): 397-406 (1992)

Wojciech Maly: What is Design for Manufacturability (DFM)? (Panel Abstract). DAC 1991: 252

Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske: Stuck Fault and Current Testing Comparison Using CMOS Chip Test. ITC 1991: 311-318

Anne Meixner, Wojciech Maly: Fault Modeling for the Testing of Mixed Integrated Circuits. ITC 1991: 564-572

Wojciech Maly: Improving the Quality of Test Education. ITC 1991: 1119

Phil Nigh, Wojciech Maly: Test Generation for Current Testing (CMOS ICs). IEEE Design & Test of Computers 7(1): 26-38 (1990)

Wojciech Maly: Current testing. ITC 1990: 257

Thomas M. Storey, Wojciech Maly: CMOS bridging fault detection. ITC 1990: 842-851

Thomas M. Storey, Wojciech Maly: CMOS Bridging Fault Detection. ITC 1990: 1123-1132

Wojciech Maly, Samir B. Naik: Process Monitoring Oriented IC Testing. ITC 1989: 527-532

Wojciech Maly: Realistic Fault Modeling for VLSI Testing. DAC 1987: 173-180

Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director: VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 114-130 (1986)

Wojciech Maly: Optimal order of the VLSI IC testing sequence. DAC 1986: 560-566

Wojciech Maly, Zygmunt Pizlo: Tolerance Assignment for IC Selection Tests. IEEE Trans. on CAD of Integrated Circuits and Systems 4(2): 156-162 (1985)

Wojciech Maly: Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 166-177 (1985)

Wojciech Maly, F. Joel Ferguson, John Paul Shen: Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC 1984: 390-399

Wojciech Maly, Andrzej J. Strojwas: Statistical Simulation of the IC Manufacturing Process. IEEE Trans. on CAD of Integrated Circuits and Systems 1(3): 120-131 (1982)