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 | 2012 | |
|---|---|---|
| j4 |      | Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm: Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 271-284 (2012) |
| c10 | | Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita: On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700 |
| c9 | | Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris: Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE 2012: 629-634 |
| 2011 | ||
| c8 | | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour: Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD 2011: 587-594 |
| 2010 | ||
| j3 | | Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti: Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers 59(7): 981-994 (2010) |
| c7 | | Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus: Leveraging dominators for preprocessing QBF. DATE 2010: 1695-1700 |
| 2008 | ||
| j2 | | Marco Benedetti, Hratch Mangassarian: QBF-Based Formal Verification: Experience and Perspectives. JSAT 5(1-4): 133-191 (2008) |
| c6 | | Brian Keng, Hratch Mangassarian, Andreas G. Veneris: A succinct memory model for automated design debugging. ICCAD 2008: 137-142 |
| 2007 | ||
| j1 | | Hratch Mangassarian, Hassan Artail: A general framework for subjective information extraction from unstructured English text. Data Knowl. Eng. 62(2): 352-367 (2007) |
| c5 | | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian: Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937 |
| c4 | | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 |
| c3 | | Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah: Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19 |
| c2 | | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith: A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245 |
| 2005 | ||
| c1 | | Hratch Mangassarian, Mohab Anis: On Statistical Timing Analysis with Inter- and Intra-Die Variations. DATE 2005: 132-137 |
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