Salvador Manich

Salvador Manich, Markus S. Wamser, Georg Sigl: Detection of probing attempts in secure ICs. HOST 2012: 134-139

S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich: Design and implementation of Automatic Test Equipment IP module. European Test Symposium 2010: 244

Salvador Manich, L. Garcia-Deiros, Joan Figueras: Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007)

Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras: On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electronic Testing 20(4): 345-355 (2004)

Salvador Manich, L. García, L. Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras: BIST Technique by Equally Spaced Test Vector Sequences. VTS 2004: 206-216

Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez: Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS 2003: 80-89

Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras: RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823

Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos: Low Power BIST by Filtering Non-Detecting Vectors. J. Electronic Testing 16(3): 193-202 (2000)

Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113

Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras: Fault-Secure Parity Prediction Arithmetic Operators. IEEE Design & Test of Computers 14(2): 60-71 (1997)

Salvador Manich, Joan Figueras: Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC 1997: 597-602

Salvador Manich, Michael Nicolaidis, Joan Figueras: Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring. VTS 1996: 124-129