Erik Jan Marinissen

Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne: Design issues in heterogeneous 3D/2.5D integration. ASP-DAC 2013: 403-410

Erik Jan Marinissen: Pioneering in Asia With the US Venture Capital Model. IEEE Design & Test of Computers 29(6): 52-55 (2012)

Erik Jan Marinissen, Yervant Zorian: Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits. J. Electronic Testing 28(1): 13-14 (2012)

Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen: Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. J. Electronic Testing 28(1): 15-25 (2012)

Erik Jan Marinissen, Chun-Chuan Chi, Mario H. Konijnenburg, Jouke Verbree: A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper. J. Electronic Testing 28(1): 73-92 (2012)

Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen: Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electronic Testing 28(1): 103-120 (2012)

Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl: EDA solutions to new-defect detection in advanced process technologies. DATE 2012: 123-128

Erik Jan Marinissen: Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. DATE 2012: 1277-1282

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen: DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10

Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree: Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1705-1718 (2011)

Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario H. Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel: Automation of 3D-DfT Insertion. Asian Test Symposium 2011: 395-400

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu: Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu: DfT Architecture for 3D-SICs with Multiple Towers. European Test Symposium 2011: 51-56

Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu: Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10

Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel: Evaluation of TSV and micro-bump probing for wide I/O testing. ITC 2011: 1-10

Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens: Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism. J. Electronic Testing 26(4): 453-464 (2010)

Erik Jan Marinissen, Chun-Chuan Chi, Jouke Verbree, Mario H. Konijnenburg: 3D DfT architecture for pre-bond and post-bond testing. 3DIC 2010: 1-8

Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne: Cost effectiveness of 3D integration options. 3DIC 2010: 1-6

Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen: Test Cost Analysis for 3D Die-to-Wafer Stacking. Asian Test Symposium 2010: 435-441

Erik Jan Marinissen, Adit Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli: Adapting to adaptive testing. DATE 2010: 556-561

Erik Jan Marinissen: Testing TSV-based three-dimensional stacked ICs. DATE 2010: 1689-1694

Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree: Test-architecture optimization for TSV-based 3D stacked ICs. European Test Symposium 2010: 24-29

Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis: On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. European Test Symposium 2010: 36-41

Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal: 3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217

Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen: On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. ITC 2010: 183-192

Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen: Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. ITC 2010: 193-201

Erik Jan Marinissen, Jouke Verbree, Mario H. Konijnenburg: A structured and scalable test access architecture for TSV-based 3D stacked ICs. VTS 2010: 269-274

Erik Jan Marinissen, Yervant Zorian: Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Design & Test of Computers 26(1): 6-7 (2009)

Erik Jan Marinissen, Yervant Zorian: IEEE Std 1500 Enables Modular SoC Testing. IEEE Design & Test of Computers 26(1): 8-17 (2009)

Erik Jan Marinissen, Yervant Zorian: Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. IEEE Design & Test of Computers 26(3): 4 (2009)

Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick: Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Design & Test of Computers 26(3): 25-37 (2009)

Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty: Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009)

Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne: Impact of 3D design choices on manufacturing cost. 3DIC 2009: 1-5

Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson: On Scan Chain Diagnosis for Intermittent Faults. Asian Test Symposium 2009: 47-54

Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol: Contactless testing: Possibility or pipe-dream? DATE 2009: 676-681

Erik Jan Marinissen, Yervant Zorian: Testing 3D chips containing through-silicon vias. ITC 2009: 1-11

Rob Aitken, Erik Jan Marinissen: Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. IEEE Design & Test of Computers 25(3): 206-207 (2008)

Erik Jan Marinissen: Bugs, moths, grasshoppers, and whales. IEEE Design & Test of Computers 25(3): 288 (2008)

Ozgur Sinanoglu, Erik Jan Marinissen: Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE 2008: 182-187

Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev, Kees Goossens: Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism. European Test Symposium 2008: 21-26

Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici: DATE 07 workshop on diagnostic services in NoCs. IEEE Design & Test of Computers 24(5): 510 (2007)

Christian Landrault, Erik Jan Marinissen: Editorial. IET Computers & Digital Techniques 1(3): 145 (2007)

Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes: Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Computers & Digital Techniques 1(3): 197-206 (2007)

Erik Jan Marinissen, Nicola Nicolici: Editorial Silicon Debug and Diagnosis. IET Computers & Digital Techniques 1(6): 659-660 (2007)

Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters: Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. DATE 2007: 853-858

Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters: Test quality analysis and improvement for an embedded asynchronous FIFO. DATE 2007: 859-864

Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke: Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. ITC 2007: 1-10

Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. CoRR abs/0710.4687 (2007)

Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar: Conference Reports. IEEE Design & Test of Computers 23(4): 262-265 (2006)

Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290

Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes: Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. European Test Symposium 2006: 213-218

Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electronic Testing 21(1): 17-31 (2005)

Tom Waayers, Erik Jan Marinissen, Maurice Lousberg: IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. Asian Test Symposium 2005: 450

Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE 2005: 44-49

Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian: Challenges in Embedded Memory Design and Test. DATE 2005: 722-727

Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE 2004: 108-113

Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge: Trends in Testing Integrated Circuits. ITC 2004: 688-697

Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212

Erik Jan Marinissen: Security vs. Test Quality: Can We Really Only Have One at a Time? ITC 2004: 1411

Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts: Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Design & Test of Computers 20(2): 8-18 (2003)

Sandeep Kumar Goel, Erik Jan Marinissen: A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electronic Testing 19(4): 425-435 (2003)

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003)

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient test access mechanism optimization for system-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 635-643 (2003)

Sandeep Kumar Goel, Erik Jan Marinissen: SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003)

Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller: Creating Value Through Test. DATE 2003: 10402-10409

Sandeep Kumar Goel, Erik Jan Marinissen: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE 2003: 10738-10741

Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen: Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC 2003: 369-378

Krishnendu Chakrabarty, Erik Jan Marinissen: How Useful are the ITC 02 SoC Test Benchmarks? IEEE Design & Test of Computers 19(5): 120, 119 (2002)

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electronic Testing 18(2): 213-230 (2002)

Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian: On IEEE P1500's Standard for Embedded Core Test. J. Electronic Testing 18(4-5): 365-383 (2002)

Erik Jan Marinissen: The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. J. Electronic Testing 18(4-5): 435-454 (2002)

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320-

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498

Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty: A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528

Sandeep Kumar Goel, Erik Jan Marinissen: Effective and Efficient Test Architecture Design for SOCs. ITC 2002: 529-538

Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258

Sandeep Kumar Goel, Erik Jan Marinissen: Cluster-Based Test Architecture Design for System-on-Chip. VTS 2002: 259-264

Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich: Application of Deterministic Logic BIST on Industrial Circuits. J. Electronic Testing 17(3-4): 351-362 (2001)

Erik Jan Marinissen: An Industrial Approach to Core-Based System Chip Testing. VLSI-SOC 2001: 389-400

Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032

Yervant Zorian, Erik Jan Marinissen: System chip test: how will it impact your design? DAC 2000: 136-141

Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen: Application of deterministic logic BIST on industrial circuits. ITC 2000: 105-114

Yervant Zorian, Erik Jan Marinissen, Rohit Kapur: On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777

Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel: Wrapper design for embedded core test. ITC 2000: 911-920

Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing Embedded-Core-Based System Chips. IEEE Computer 32(6): 52-60 (1999)

Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. ITC 1999: 616-627

Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing embedded-core based system chips. ITC 1998: 130-143

Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters: A structured and scalable mechanism for test access to embedded reusable cores. ITC 1998: 284-293

Joep Aerts, Erik Jan Marinissen: Scan chain design for test time reduction in core-based ICs. ITC 1998: 448-457