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Zied Marrakchi
2010 – today
- 2013
[c25]Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez: Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC 2013: 197-209- [c24]Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid: Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. ARC 2013: 210-217
- [c23]Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez: Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. ARC 2013: 221
- [c22]Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi: Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI 2013: 335-336
- 2012
- [j4]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi: A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. Microprocessors and Microsystems - Embedded Hardware Design 36(8): 588-605 (2012)
- [c21]Mariem Turki, Habib Mehrez, Zied Marrakchi: Multi-FPGA prototyping environment: Large benchmark generation and signals routing. ReConFig 2012: 1-6
- 2011
- [j3]Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi: Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfig. Comp. 2011 (2011)
- [j2]Husain Parvez, Zied Marrakchi, Alp Kilic, Habib Mehrez: Application-Specific FPGA using heterogeneous logic blocks. TRETS 4(3): 24 (2011)
- [c20]Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez: Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229
- [c19]Emna Amouri, Zied Marrakchi, Habib Mehrez: Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4
- 2010
- [c18]Husain Parvez, Zied Marrakchi, Habib Mehrez: Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109
- [c17]Husain Parvez, Zied Marrakchi, Habib Mehrez: Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290
2000 – 2009
- 2009
- [j1]Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez: FPGA Interconnect Topologies Exploration. Int. J. Reconfig. Comp. 2009 (2009)
- [c16]Husain Parvez, Zied Marrakchi, Habib Mehrez: ASIF: Application Specific Inflexible FPGA. FPT 2009: 112-119
- [c15]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794
- [c14]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206
- 2008
- [c13]Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez: A new coarse-grained FPGA architecture exploration environment. FPT 2008: 285-288
- [c12]Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez: Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326
- [c11]Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez: The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120
- [c10]Husain Parvez, Zied Marrakchi, Habib Mehrez: Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126
- 2007
- [c9]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez: Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT 2007: 269-272
- [c8]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez: Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252
- 2006
- [c7]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225
- [c6]Zied Marrakchi, Hayder Mrabet, Habib Mehrez: Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229
- [c5]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679
- [c4]Zied Marrakchi, Hayder Mrabet, Habib Mehrez: A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268
- [c3]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot: Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123
- 2005
- [c2]Zied Marrakchi, Hayder Mrabet, Habib Mehrez: Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005
- [c1]Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot: Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62
Coauthor Index
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last updated on 2013-06-04 22:22 CEST by the dblp team