José F. Martínez

Miguel S. Familiar, José F. Martínez, Iván Corredor, Carlos García-Rubio: Building service-oriented Smart Infrastructures over Wireless Ad Hoc Sensor Networks: A middleware perspective. Computer Networks 56(4): 1303-1328 (2012)

Iván Corredor, José F. Martínez, Miguel S. Familiar, Lourdes López: Knowledge-Aware and Service-Oriented Middleware for deploying pervasive services. J. Network and Computer Applications 35(2): 562-576 (2012)

Janani Mukundan, José F. Martínez: MORSE: Multi-objective reconfigurable self-optimizing memory scheduler. HPCA 2012: 65-76

Janani Mukundan, Saugata Ghose, Robert Karmazin, Engin Ipek, José F. Martínez: Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture. ICS 2012: 101-110

Marc Roelands, Johan Plomp, Diego Casado Mansilla, Juan R. Velasco, Ismail Salhi, Gyu Myoung Lee, Noël Crespi, Filipe Vinci dos Santos, Julien Vachaudez, Frédéric Bettens, Joel Hanqc, Carlos Valderrama, Nilo Menezes, Alexandre Girardi, Xavier Ricco, Mario Lopez-Ramos, Nicolas Dumont, Iván Corredor, Miguel S. Familiar, José F. Martínez, Vicente Hernández, Dries De Roeck, Christof van Nimwegen, Leire Bastida, Marisa Escalante, Juncal Alonso, Quentin Reul, Yan Tang, Robert Meersman: The DiY Smart Experiences Project - A European Endeavour Removing Barriers for User-generated Internet of Things Applications. Architecting the Internet of Things 2011: 279-315

Nevin Kirman, José F. Martínez: A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. ASPLOS 2010: 15-28

José F. Martínez, Engin Ipek: Dynamic Multicore Resource Management: A Machine Learning Approach. IEEE Micro 29(5): 8-17 (2009)

David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez (Eds.): 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA. ACM 2009, isbn 978-1-60558-798-1

Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana: Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. ISCA 2008: 39-50

Ramazan Bitirgen, Engin Ipek, José F. Martínez: Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. MICRO 2008: 318-329

Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi: On-Chip Optical Technology in Future Bus-Based Multicore Designs. IEEE Micro 27(1): 56-66 (2007)

Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar: Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. DSN 2007: 317-326

Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez: A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. IPDPS 2007: 1-6

Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez: Core fusion: accommodating software diversity in chip multiprocessors. ISCA 2007: 186-197

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez: Scavenger: A New Last Level Cache Architecture with Global Block Priority. MICRO 2007: 421-432

Jian Li, José F. Martínez: Dynamic power-performance adaptation of parallel computation on chip multiprocessors. HPCA 2006: 77-87

Engin Ipek, José F. Martínez, Bronis R. de Supinski, Sally A. McKee, Martin Schulz: Dynamic program phase detection in distributed shared-memory multiprocessors. IPDPS 2006

Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi: Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. MICRO 2006: 492-503

Jian Li, José F. Martínez: Power-performance considerations of parallel computing on chip multiprocessors. TACO 2(4): 397-422 (2005)

Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez: Checkpointed Early Load Retirement. HPCA 2005: 16-27

Jian Li, José F. Martínez: Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors. ISPASS 2005: 124-134

Meyrem Kirman, Nevin Kirman, José F. Martínez: Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. MICRO 2005: 245-256

José A. Santos, Ariel Carrasco, José F. Martínez: Feature Selection Using Typical Testors Applied to Estimation of Stellar Parameters. Computación y Sistemas 8(1) (2004)

Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero: A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. SIGARCH Computer Architecture News 32(3): 3-10 (2004)

Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez: Toward kilo-instruction processors. TACO 1(4): 389-417 (2004)

Jian Li, José F. Martínez, Michael C. Huang: The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. HPCA 2004: 14-23

Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero: A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2 (2003)

José F. Martínez, Josep Torrellas: Speculative Synchronization: Programmability and Performance for Parallel Codes. IEEE Micro 23(6): 126-134 (2003)

José F. Martínez, Josep Torrellas: Speculative synchronization: applying thread-level speculation to explicitly parallel applications. ASPLOS 2002: 18-29

José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas: Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO 2002: 3-14

Marcelo H. Cintra, José F. Martínez, Josep Torrellas: Architectural support for scalable speculative parallelization in shared-memory multiprocessors. ISCA 2000: 13-24

M. C. Fernández, O. Delgado, J. I. López, M. A. Luna, José F. Martínez, J. F. B. Pardo, J. M. Peña: DAMISYS: An Overview. DaWaK 1999: 313-317

José F. Martínez, Josep Torrellas, José Duato: Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. International Conference on Supercomputing 1999: 202-209

Juan Carlos Fernández, Lourdes Peñalver, M. Sobejano, José F. Martínez, Vicente Hernández, Josep Tornero: An Interface Based on Transputers to Simulate the Dynamic Equation of Robot Manipulators Using Parallel Computing. VECPAR 1996: 365-379