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 | 2013 | |
|---|---|---|
| j18 |      | Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins: A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW. J. Solid-State Circuits 48(2): 527-540 (2013) |
| c50 | | Zhicheng Lin, Pui-In Mak, Rui Paulo Martins: A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS. ISSCC 2013: 448-449 |
| 2012 | ||
| j17 | | Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. J. Solid-State Circuits 47(11): 2614-2626 (2012) |
| j16 | | He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. J. Solid-State Circuits 47(11): 2763-2772 (2012) |
| j15 | | Chio-In Ieong, Pui-In Mak, Chi-Pang Lam, Cheng Dong, Mang-I. Vai, Peng Un Mak, Sio-Hang Pun, Feng Wan, Rui Paulo Martins: A 0.83-$\mu {\rm W}$ QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35- $\mu{\rm m}$ CMOS. IEEE Trans. Biomed. Circuits and Systems 6(6): 586-595 (2012) |
| c49 | | Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins: A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS 2012: 29-32 |
| c48 | | Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins: A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS 2012: 33-36 |
| c47 | | Yinsidi Jiao, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins: A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation. APCCAS 2012: 148-151 |
| c46 | | Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins: A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS 2012: 268-271 |
| c45 | | Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC 2012: 1-4 |
| c44 | | Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins: A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC 2012: 265-268 |
| c43 | | Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins: A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC 2012: 377-380 |
| c42 | | Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS 2012: 65-68 |
| c41 | | Miguel A. Martins, Pui-In Mak, Rui Paulo Martins: A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier. ISCAS 2012: 472-475 |
| c40 | | Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins: A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW. ISSCC 2012: 368-370 |
| 2011 | ||
| j14 | | Pui-In Mak, Rui Paulo Martins: A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS. J. Solid-State Circuits 46(9): 1970-1984 (2011) |
| c39 | | U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 |
| c38 | | Weng-Fai Cheng, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins: A highly-linear ultra-wideband balun-LNA for cognitive radios. EUROCON 2011: 1-4 |
| c37 | | Miao Liu, Pui-In Mak, Zushu Yan, Rui Paulo Martins: A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies. ISCAS 2011: 33-36 |
| c36 | | Miguel A. Martins, Pui-In Mak, Rui Paulo Martins: A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance. ISCAS 2011: 289-292 |
| c35 | | Pui-In Mak, Rui Paulo Martins: A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS. ISSCC 2011: 172-174 |
| c34 | | He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 |
| 2010 | ||
| j13 | | Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins: 1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits, Devices & Systems 4(1): 1-13 (2010) |
| j12 | | Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. J. Solid-State Circuits 45(6): 1111-1121 (2010) |
| j11 | | He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. on Circuits and Systems 57-II(1): 16-20 (2010) |
| j10 | | Ka-Fai Un, Pui-In Mak, Rui Paulo Martins: Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications. IEEE Trans. on Circuits and Systems 57-I(5): 970-981 (2010) |
| j9 | | U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti: Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. on Circuits and Systems 57-II(8): 607-611 (2010) |
| j8 | | Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010 (2010) |
| c33 | | Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS 2010: 547-550 |
| c32 | | Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang: An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS 2010: 878-881 |
| c31 | | Miguel A. Martins, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins: SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit. ISCAS 2010: 1276-1279 |
| c30 | | Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064 |
| 2009 | ||
| j7 | | Pui-In Mak, Rui Paulo Martins: Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners. IEEE Trans. on Circuits and Systems 56-I(5): 933-942 (2009) |
| c29 | | Ka-Fai Un, Pui-In Mak, Rui Paulo Martins: An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners. ISCAS 2009: 433-436 |
| c28 | | Chon-Teng Ma, Pui-In Mak, Mang I Vai, Peng Un Mak, Sio-Hang Pun, Feng Wan, Rui Paulo Martins: A 90nm CMOS Bio-potential Signal Readout Front-end with Improved Powerline Interference Rejection. ISCAS 2009: 665-668 |
| 2008 | ||
| j6 | | Pui-In Mak, Seng-Pan U., Rui Paulo Martins: On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. IEEE Trans. on Circuits and Systems 55-I(2): 496-509 (2008) |
| j5 | | Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins: Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. on Circuits and Systems 55-II(7): 648-652 (2008) |
| j4 | | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. on Circuits and Systems 55-I(8): 2188-2201 (2008) |
| c27 | | He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS 2008: 5-8 |
| c26 | | Pui-In Mak, Ka-Hou Ao Ieong, Rui Paulo Martins: An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. ISCAS 2008: 668-671 |
| 2007 | ||
| j3 | | Pui-In Mak, Seng-Pan U, Rui Paulo Martins: Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. IET Circuits, Devices & Systems 1(6): 415-426 (2007) |
| j2 | | Phillip Ngai Cheong, Rui Paulo Martins: Interactive IIR SC Multirate Compiler Applied to Multistage decimator Design. Journal of Circuits, Systems, and Computers 16(4): 517-525 (2007) |
| c25 | | Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. ISCAS 2007: 1947-1950 |
| 2006 | ||
| c24 | | Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins: A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. APCCAS 2006: 183-186 |
| c23 | | Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins: A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. ISCAS 2006 |
| c22 | | Chon-In Lao, Seng-Pan U., Rui Paulo Martins: A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. ISCAS 2006 |
| c21 | | Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS 2006 |
| c20 | | Pui-In Mak, Seng-Pan U., Rui Paulo Martins: Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. ISCAS 2006 |
| c19 | | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS 2006 |
| 2005 | ||
| c18 | | Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. ISCAS (1) 2005: 392-395 |
| c17 | | Si-Weng Fok, Phillip Ngai Cheong, Kam-Weng Tam, Rui Paulo Martins: A novel microstrip bandpass filter design using asymmetric parallel coupled-line. ISCAS (1) 2005: 404-407 |
| c16 | | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) 2005: 1581-1584 |
| c15 | | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) 2005: 1585-1588 |
| c14 | | Chon-In Lao, Seng-Pan U., Rui Paulo Martins: A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. ISCAS (4) 2005: 3095-3098 |
| c13 | | Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins: A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. ISCAS (4) 2005: 3099-3102 |
| 2004 | ||
| j1 | | Seng-Pan U., Sai-Weng Sin, Rui Paulo Martins: Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. IEEE T. Instrumentation and Measurement 53(4): 1279-1288 (2004) |
| c12 |  | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) 2004: 369-372 |
| c11 | | Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. ISCAS (4) 2004: 417-420 |
| c10 | | Sio-Weng Ting, Kam-Weng Tam, Rui Paulo Martins: Novel interdigital microstrip bandpass filter with improved spurious response. ISCAS (1) 2004: 984-987 |
| c9 | | Pui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins: An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. ISCAS (1) 2004: 1068-1071 |
| 2003 | ||
| c8 | | Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca: Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) 2003: 129-132 |
| c7 | | Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins: A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. ISCAS (1) 2003: 1061-1064 |
| 2002 | ||
| c6 | | Seng-Pan U., Rui Paulo Martins, José E. Franca: Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. ISCAS (4) 2002: 441-444 |
| 2001 | ||
| c5 | | Seng-Pan U., Rui Paulo Martins, José E. Franca: High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. ISCAS (1) 2001: 204-207 |
| c4 | | Seng-Pan U., Rui Paulo Martins, José E. Franca: A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. ISCAS (1) 2001: 320-323 |
| 1999 | ||
| c3 | | Kam-Weng Tam, P. Viror, J. C. Freire, Rui Paulo Martins: New microwave bandstop filter using lumped and transversal network. ISCAS (6) 1999: 30-32 |
| c2 | | Seng-Pan U., Rui Paulo Martins, José E. Franca: Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. ISCAS (2) 1999: 57-60 |
| c1 | | Seng-Pan U., Rui Paulo Martins, José E. Franca: High performance multirate SC circuits with predictive correlated double sampling technique. ISCAS (2) 1999: 77-80 |
Colors in the list of coauthors
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