Guido Masera

Bin Wu, Guido Masera: Analysis on parallel implementations of fixed-complexity sphere decoder. SCIENCE CHINA Information Sciences 56(4): 1-11 (2013)

Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca: Power Control for Crossbar-Based Input-Queued Switches. IEEE Trans. Computers 62(1): 74-82 (2013)

Simone Zezza, Saeid Nooshabadi, Guido Masera: A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. IEEE Trans. on Circuits and Systems 60-I(4): 951-964 (2013)

Carlo Condo, Amer Baghdadi, Guido Masera: A joint communication and application simulator for NoC-based SoCs. CoRR abs/1301.1465 (2013)

M. Tamagnone, Maurizio Martina, Guido Masera: An application specific instruction set processor based implementation for signal detection in multiple antenna systems. Microprocessors and Microsystems - Embedded Hardware Design 36(3): 245-256 (2012)

Maurizio Martina, Guido Masera, Stylianos Papaharalabos, P. Takis Mathiopoulos, Fotios Gioulekas: On Practical Implementation and Generalizations of max^* Operator for Turbo and LDPC Decoders. IEEE T. Instrumentation and Measurement 61(4): 888-895 (2012)

Luca Gaetano Amarù, Maurizio Martina, Guido Masera: High Speed Architectures for Finding the First two Maximum/Minimum Values. IEEE Trans. VLSI Syst. 20(12): 2342-2346 (2012)

Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera: A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. VLSI Design 2012 (2012)

Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy: Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012 (2012)

Carlo Condo, Maurizio Martina, Guido Masera: A Network-on-Chip-based turbo/LDPC decoder architecture. DATE 2012: 1525-1530

Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi: On chip interconnects for multiprocessor turbo decoding architectures. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 167-181 (2011)

Maurizio Martina, Guido Masera: State Metric Compression Techniques for Turbo Decoder Architectures. IEEE Trans. on Circuits and Systems 58-I(5): 1119-1128 (2011)

Muhammad Awais, Ashwani Singh, Guido Masera: Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications. ACC (2) 2011: 374-385

Carlo Condo, Guido Masera: A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. DASIP 2011: 261-268

Muhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera: A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder. DSD 2011: 340-347

Maurizio Martina, Guido Masera: Improving Network-on-Chip-based turbo decoder architectures. CoRR abs/1105.1014 (2011)

Carlo Condo, Guido Masera: A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture. CoRR abs/1105.2624 (2011)

Maurizio Martina, Guido Masera, Gianluca Piccinini: Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits, Devices & Systems 4(2): 159-167 (2010)

Sergio Saponara, Maurizio Martina, Michele Casula, Luca Fanucci, Guido Masera: Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding. Microprocessors and Microsystems - Embedded Hardware Design 34(7-8): 316-328 (2010)

Maurizio Martina, Guido Masera: Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures. IEEE Trans. on Circuits and Systems 57-I(10): 2776-2789 (2010)

Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera: ALOE-Based Flexible LDPC Decoder. DSD 2010: 314-320

Bin Wu, Guido Masera: A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder. DSD 2010: 737-744

Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca: Thermal Control for Crossbar-Based Input-Queued Switches. GLOBECOM 2010: 1-5

Maurizio Martina, Guido Masera: VLSI Architectures for WIMAX Channel Decoders. CoRR abs/1001.4694 (2010)

Bin Wu, Guido Masera: A Novel VLSI Architecture of Fixed-complexity Sphere Decoder. CoRR abs/1006.4030 (2010)

Ashwani Singh, A. Al Ghouwayel, Guido Masera, Emmanuel Boutillon: A new performance evaluation metric for sub-optimal iterative decoders. IEEE Communications Letters 13(7): 513-515 (2009)

Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera, Maurizio Martina: On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator. IEEE Communications Letters 13(7): 522-524 (2009)

Maurizio Martina, Mario Nicola, Guido Masera: Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder. Journal of Circuits, Systems, and Computers 18(3): 535-564 (2009)

Andrea Molino, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Terreno, Giorgio Pasquettaz, Giuseppe D'Angelo: FPGA implementation of time-frequency analysis algorithms for laser welding monitoring. Microprocessors and Microsystems - Embedded Hardware Design 33(3): 179-190 (2009)

Simone Zezza, Saeid Nooshabadi, Maurizio Martina, Guido Masera: Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000. IEEE Trans. Circuits Syst. Video Techn. 19(4): 591-596 (2009)

Barbara Cerato, Guido Masera, Emanuele Viterbo: Decoding the Golden Code: A VLSI Design. IEEE Trans. VLSI Syst. 17(1): 156-160 (2009)

Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel: Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD 2009: 582-589

Simone Zezza, Guido Masera, Saeid Nooshabadi: A feasible VLSI engine for soft-input-soft-output for joint source channel codes. ICIP 2009: 2669-2672

Maurizio Martina, Guido Masera: Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures. CoRR abs/0909.1876 (2009)

Barbara Cerato, Guido Masera, Emanuele Viterbo: Decoding the golden space-time trellis coded modulation. IEEE Communications Letters 12(8): 569-571 (2008)

Maurizio Martina, Mario Nicola, Guido Masera: Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding. IEEE Communications Letters 12(11): 846-848 (2008)

Fabrizio Vacca, Libero Dinoi, Guido Masera: Design of a VLSI Decoder for Partially Structured LDPC Codes. Int. J. Digital Multimedia Broadcasting 2008 (2008)

Maurizio Martina, Mario Nicola, Guido Masera: A Flexible UMTS-WiMax Turbo Decoder Architecture. IEEE Trans. on Circuits and Systems 55-II(4): 369-373 (2008)

Maurizio Martina, Guido Masera: Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]. IEEE Trans. on Circuits and Systems 55-II(5): 494 (2008)

Barbara Cerato, Guido Masera, Emanuele Viterbo: Enabling VLSI Processing Blocks for MIMO-OFDM Communications. VLSI Design 2008 (2008)

Simone Zezza, Guido Masera: VLSI implementation of SISO arithmetic decoders for joint source channel coding. DATE 2008: 1075-1078

Simone Zezza, Maurizio Martina, Guido Masera, Saeid Nooshabadi: Error resilient JPEG2000 decoding for wireless applications. ICIP 2008: 2016-2019

Maurizio Martina, Andrea Terreno, Fabrizio Vacca, Andrea Molino, Guido Masera, Giuseppe D'Angelo, Giorgio Pasquettaz: Real-time implementation of a time-frequency analysis scheme. ACM Great Lakes Symposium on VLSI 2007: 180-183

Maurizio Martina, Guido Masera: Flexible blocks for high throughput serially concatenated convolutional codes. ACM Great Lakes Symposium on VLSI 2007: 184-187

Barbara Cerato, Guido Masera, Peter Nilsson: Hardware architecture for matrix factorization in mimo receivers. ACM Great Lakes Symposium on VLSI 2007: 196-199

Alberto Dassatti, Simone Zezza, Mario Nicola, Guido Masera: Beyond 3G wireless communication system prototype. ACM Great Lakes Symposium on VLSI 2007: 335-340

Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda: Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. CoRR abs/0710.4840 (2007)

Barbara Cerato, Guido Masera, Emanuele Viterbo: Decoding the Golden Code: a VLSI design. CoRR abs/0711.2383 (2007)

Maurizio Martina, Guido Masera: Mumford and Shah Functional: VLSI Analysis and Implementation. IEEE Trans. Pattern Anal. Mach. Intell. 28(3): 487-494 (2006)

Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51

Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera: Interconnection framework for high-throughput, flexible LDPC decoders. DATE Designers' Forum 2006: 124-129

Giorgio Pioppo, Rashid Ansari, Ashfaq A. Khokhar, Guido Masera: Low-Complexity Video Compression Combining Adaptive Multifoveation and Reuse of High-Resolution Information. ICIP 2006: 3153-3156

Simone Zezza, Marco Grangetto, Maurizio Martina, Fabrizio Vacca, Guido Masera: Error correcting arithmetic coding for JPEG 2000: memory and performance analysis. MobiMedia 2006: 3

Mario Nicola, Alberto Dassatti, Guido Masera, Andrea Concil, Angelo Poloni: Mixed hardware-software testbed for IEEE-802.11n. TRIDENTCOM 2006

Alberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni: High Performance Channel Model Hardware Emulator for 802.11n. FPT 2005: 303-304

Maurizio Martina, Guido Masera: Low-complexity, efficient 9/7 wavelet filters implementation. ICIP (3) 2005: 1000-1003

Andrea Molino, Fabrizio Vacca, Guido Masera: Optimized CORDIC core for frequency-domain motion estimation. ICIP (3) 2005: 1072-1075

Andrea Molino, Fabrizio Vacca, Guido Masera: Design and implementation of phase correlation based motion estimator. SoCC 2005: 291-294

Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectronics Journal 35(10): 849-857 (2004)

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. VLSI Syst. 12(4): 349-358 (2004)

Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda: Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. DATE 2004: 228-233

Maurizio Martina, Guido Masera: A statistical model for estimating the effect of process variations on crosstalk noise. SLIP 2004: 115-120

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Coupled electro-thermal modeling and optimization of clock networks. Microelectronics Journal 34(12): 1175-1185 (2003)

Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. VLSI Signal Processing 35(2): 137-153 (2003)

Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni: Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA 2003: 246

Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100

M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130

Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni: Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. VLSI Syst. 10(3): 279-285 (2002)

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni: Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL 2002: 332-339

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni: Reconfigurable DSP IP for multimedia applications. ICASSP 2002: 4179

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni: Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208

Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290

Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Hierarchical power supply noise evaluation for early power grid design prediction. SLIP 2001: 183-188

Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design 2001: 524-530

F. Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni: A 50 Mbit/s Iterative Turbo-Decoder. DATE 2000: 176-180

Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Noise Safety Design Methodologies. ISQED 2000: 157-

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni: VLSI architectures for turbo codes. IEEE Trans. VLSI Syst. 7(3): 369-379 (1999)

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni: A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics 1999: 51-54

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni: New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI 1999: 82-85

Mariana-Eugenia Petre, Guido Masera: A Parametrical Architecture for Reed-Solomon Decoders. Great Lakes Symposium on VLSI 1996: 81-