Yusuke Matsunaga

Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Transactions 94-A(12): 2579-2586 (2011)

Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga: A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT 2011: 268-276

Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156

Taiga Takata, Yusuke Matsunaga: A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS 2011: 246-251

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED 2011: 217-222

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC 2010: 337-342

Taiga Takata, Yusuke Matsunaga: A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA 2010: 289

Taiga Takata, Yusuke Matsunaga: Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Transactions 92-A(12): 3268-3275 (2009)

Taiga Takata, Yusuke Matsunaga: An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356

Tsuyoshi Sadakata, Yusuke Matsunaga: A Behavioral Synthesis Method with Special Functional Units. IEICE Transactions 91-A(4): 1084-1091 (2008)

Makoto Sugihara, Yusuke Matsunaga, Kazuaki Murakami: Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Transactions 91-A(12): 3451-3460 (2008)

Tsuyoshi Sadakata, Yusuke Matsunaga: An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. ASP-DAC 2008: 32-35

Taiga Takata, Yusuke Matsunaga: Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC 2008: 144-147

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Synthesis of parallel prefix adders considering switching activities. ICCD 2008: 404-409

Yusuke Matsunaga: Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. IEICE Transactions 90-A(4): 705-706 (2007)

Tsuyoshi Sadakata, Yusuke Matsunaga: A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. IEICE Transactions 90-A(4): 792-799 (2007)

Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki Murakami: Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Transactions 90-C(5): 1012-1020 (2007)

Yusuke Matsunaga: Special Section on VLSI Design and CAD Algorithms. IEICE Transactions 90-A(12): 2649-2650 (2007)

Taeko Matsunaga, Yusuke Matsunaga: Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Transactions 90-A(12): 2770-2777 (2007)

Taeko Matsunaga, Yusuke Matsunaga: Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI 2007: 435-440

Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Transactions 89-C(3): 377-383 (2006)

Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006

Hiroyuki Higuchi, Yusuke Matsunaga: Enhancing the performance of multi-cycle path analysis in an industrial setting. ASP-DAC 2004: 192-197

Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga: Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186

Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga: The statistical longest path problem and its application to delay analysis of logical circuits. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 134-139

Yusuke Matsunaga: On accelerating pattern matching for technology mapping. ICCAD 1998: 118-122

Hiroyuki Higuchi, Yusuke Matsunaga: A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. DAC 1996: 463-466

Yusuke Matsunaga: An Efficient Equivalence Checker for Combinational Circuits. DAC 1996: 629-634

Yusuke Matsunaga: A New Algorithm for Boolean Matching Utilizing Structural Information. IEICE Transactions 78-D(3): 219-223 (1995)

Hiroyuki Higuchi, Yusuke Matsunaga: Implicit prime compatible generation for minimizing incompletely specified finite state machines. ASP-DAC 1995

Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita: LP based cell selection with constraints of timing, area, and power consumption. ICCAD 1994: 378-381

Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga: Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 6-12 (1993)

Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton: On Computing the Transitive Closure of a State Transition Relation. DAC 1993: 260-265

Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita: A Resynthesis Approach for Network Optimization. DAC 1991: 458-463

Masahiro Fujita, Yusuke Matsunaga: Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD 1991: 560-563

Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita: Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC 1990: 284-289

Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda: Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41

Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda: Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409

Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato: co-LODEX: A Cooperative Expert System for Logic design. FGCS 1988: 1299-1306

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki: A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 466-476 (1986)