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 | 2013 | |
|---|---|---|
| c36 |      | Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano: A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 |
| 2012 | ||
| j7 | | Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki: The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems. IEEE Micro 32(6): 52-61 (2012) |
| c35 | | Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano: Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS 2012: 212-224 |
| c34 | | Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 |
| c33 | | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 |
| c32 | | Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 |
| c31 | | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova: A case for random shortcut topologies for HPC interconnects. ISCA 2012: 177-188 |
| 2011 | ||
| j6 | | Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011) |
| j5 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011) |
| j4 | | Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 520-533 (2011) |
| c30 | | Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57 |
| c29 | | Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano: A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 |
| c28 | | Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki: Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor. RTCSA (2) 2011: 9-15 |
| c27 | | Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki: Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion. RTCSA (2) 2011: 22-27 |
| c26 | | Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano: A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 |
| 2010 | ||
| c25 | | Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161 |
| c24 | | José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227 |
| c23 | | Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438 |
| c22 | | Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68 |
| 2009 | ||
| j3 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 92-D(4): 575-583 (2009) |
| j2 | | Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano: Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distrib. Syst. 20(8): 1126-1141 (2009) |
| c21 | | Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano: MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 |
| c20 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 |
| c19 | | José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506 |
| c18 | | Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano: An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11 |
| c17 | | Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano: Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8 |
| c16 |  | José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295 |
| 2008 | ||
| c15 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 |
| c14 | | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 |
| c13 | | Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 |
| c12 | | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 |
| c11 | | Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 |
| 2007 | ||
| j1 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007) |
| c10 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 |
| c9 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 |
| c8 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 |
| 2006 | ||
| c7 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31 |
| c6 | | Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 |
| c5 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 |
| 2005 | ||
| c4 | | Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima: An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170 |
| c3 | | Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai: Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. ICN (2) 2005: 361-368 |
| c2 | | Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 |
| c1 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349 |
Colors in the list of coauthors
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