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 | 2013 | |
|---|---|---|
| c30 |      | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: An Architecture for IPv6 Lookup Using Parallel Index Generation Units. ARC 2013: 59-71 |
| 2012 | ||
| j11 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. IEICE Transactions 95-D(2): 364-373 (2012) |
| j10 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. Microprocessors and Microsystems - Embedded Hardware Design 36(8): 644-664 (2012) |
| j9 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. Multiple-Valued Logic and Soft Computing 19(1-3): 203-217 (2012) |
| c29 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. ARC 2012: 202-214 |
| c28 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. ISMVL 2012: 148-153 |
| 2011 | ||
| c27 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Regular Expression Matching Circuit Based on a Decomposed Automaton. ARC 2011: 16-28 |
| c26 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. ISMVL 2011: 125-130 |
| 2010 | ||
| j8 | | Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler: A Quaternary Decision Diagram Machine: Optimization of Its Code. IEICE Transactions 93-D(8): 2026-2035 (2010) |
| j7 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. IEICE Transactions 93-D(8): 2048-2058 (2010) |
| c25 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Packet Classifier Using a Parallel Branching Program Machine. DSD 2010: 745-752 |
| c24 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Comparison of Architectures for Various Decision Diagram Machines. ISMVL 2010: 229-234 |
| c23 | | Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura: A regular expression matching using non-deterministic finite automaton. MEMOCODE 2010: 73-76 |
| 2009 | ||
| c22 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC 2009: 261-267 |
| c21 | | Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura: Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. DSD 2009: 765-772 |
| c20 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: The Parallel Sieve Method for a Virus Scanning Engine. DSD 2009: 809-816 |
| c19 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: A virus scanning engine using a parallel finite-input memory machine and MPUs. FPL 2009: 635-639 |
| c18 | | Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler: A Quaternary Decision Diagram Machine and the Optimization of its Code. ISMVL 2009: 362-369 |
| 2007 | ||
| j6 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Transactions 90-D(6): 905-914 (2007) |
| j5 | | Munehiro Matsuura, Tsutomu Sasao: BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. IEICE Transactions 90-A(12): 2762-2769 (2007) |
| j4 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. Multiple-Valued Logic and Soft Computing 13(4-6): 503-520 (2007) |
| c17 | | Tsutomu Sasao, Munehiro Matsuura: An Implementation of an Address Generator Using Hash Memories. DSD 2007: 69-76 |
| c16 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A CAM Emulator Using Look-Up Table Cascades. IPDPS 2007: 1-8 |
| c15 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL 2007: 32 |
| 2006 | ||
| j3 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Transactions 89-A(12): 3471-3481 (2006) |
| c14 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A fast logic simulator using a look up table cascade emulator. ASP-DAC 2006: 466-472 |
| c13 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL 2006: 3 |
| 2005 | ||
| j2 | | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Transactions 88-A(12): 3342-3350 (2005) |
| j1 | | Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura: Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005) |
| c12 | | Tsutomu Sasao, Munehiro Matsuura: BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. DAC 2005: 373-378 |
| 2004 | ||
| c11 | | Tsutomu Sasao, Munehiro Matsuura: A method to decompose multiple-output logic functions. DAC 2004: 428-433 |
| c10 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL 2004: 302-308 |
| 2003 | ||
| c9 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Evaluation of multiple-output logic functions using decision diagrams. ASP-DAC 2003: 312-315 |
| 2002 | ||
| c8 | | Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261- |
| c7 |  | Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384 |
| 2001 | ||
| c6 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD 2001: 388-393 |
| 2000 | ||
| c5 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno: A hardware simulation engine based on decision diagrams (short paper). ASP-DAC 2000: 73-76 |
| c4 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Implementation of Multiple-Output Functions Using PQMDDs. ISMVL 2000: 199-205 |
| 1999 | ||
| c3 | | Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno: Realization of Regular Ternary Logic Functions. ASP-DAC 1999: 331- |
| 1997 | ||
| c2 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On properties of Kleene TDDs. ASP-DAC 1997: 473-476 |
| c1 | | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Decomposition of Kleene TDDs. Asian Test Symposium 1997: 234- |
| 1 | Jon T. Butler | |
| 2 | Yukihiro Iguchi | |
| 3 | Atsumu Iseno | |
| 4 | Yoshifumi Kawamura | |
| 5 | Shinobu Nagayama | |
| 6 | Hiroki Nakahara | |
| 7 | Hiroshi Nakahara | |
| 8 | Takaaki Nakamura | |
| 9 | Tsutomu Sasao |
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