Jef L. van Meerbergen

Frank Bouwens, Jos Huisken, Harmke de Groot, Martijn Bennebroek, Anteneh A. Abbo, Octavio Santana, Jef L. van Meerbergen, Antoine Fraboulet: A dual-core system solution for wearable health monitors. ACM Great Lakes Symposium on VLSI 2011: 379-382

Andreas Hansson, Benny Akesson, Jef L. van Meerbergen: Multi-processor programming in the embedded system curriculum. SIGBED Review 6(1): 9 (2009)

Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jos Hulzink, Jef L. van Meerbergen: Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring. Signal Processing Systems 57(1): 107-119 (2009)

Aleksandar Beric, Jef L. van Meerbergen, Gerard de Haan, Ramanathan Sethuraman: Memory-Centric Video Processing. IEEE Trans. Circuits Syst. Video Techn. 18(4): 439-452 (2008)

Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen: Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip. DATE 2008: 300-305

Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen: Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. HiPEAC 2008: 82-96

Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen: Decoupling of Computation and Communication with a Communication Assist. DSD 2007: 63-68

Peter Poplavko, Twan Basten, Jef L. van Meerbergen: Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism. DSD 2007: 228-235

Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen: Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model. MASCOTS 2007: 238-245

Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen: Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. SAMOS 2007: 385-395

Marco Bekooij, Maarten Wiggers, Jef L. van Meerbergen: Efficient buffer capacity and scheduler setting computation for soft real-time stream processing applications. SCOPES 2007: 1-10

Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen: Qos concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips. IEEE Trans. Consumer Electronics 52(4): 1418-1426 (2006)

Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha: Global Analysis of Resource Arbitration for MPSoC. DSD 2006: 71-78

Milan Pastrnak, Peter H. N. de With, Jef L. van Meerbergen: Realization of QoS management using negotiation algorithms for multiprocessor NoC. ISCAS 2006

Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen: Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. VLSI-SoC 2006: 80-85

Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, P. Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, F. Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan: Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. IEEE Trans. Circuits Syst. Video Techn. 15(4): 508-527 (2005)

Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen: An event-based monitoring service for networks on chip. ACM Trans. Design Autom. Electr. Syst. 10(4): 702-723 (2005)

Aleksandar Beric, Gerard de Haan, Ramanathan Sethuraman, Jef L. van Meerbergen: An Efficient Picture-Rate Up-Converter. VLSI Signal Processing 41(1): 49-63 (2005)

Aleksandar Beric, Gerard de Haan, Jef L. van Meerbergen, Ramanathan Sethuraman: Algorithm/architecture co-design of the generalized sampling theorem based de-interlacer [video signal processing]. ISCAS (3) 2005: 2943-2946

Peter Poplavko, Twan Basten, Milan Pastrnak, Jef L. van Meerbergen, Marco Bekooij, Peter H. N. de With: Extended abstract: estimation times of on-chip multiprocessor stream-oriented applications. MEMOCODE 2005: 250-251

Orlando Moreira, Jan-David Mol, Marco Bekooij, Jef L. van Meerbergen: Multiprocessor Resource Allocation for Hard-Real-Time Streaming with a Dynamic Job-Mix. IEEE Real-Time and Embedded Technology and Applications Symposium 2005: 332-341

Marco Bekooij, Jef L. van Meerbergen, Sonali Parma: Performance Guarantees by Simulation of Process Networks. SCOPES 2005: 10-19

Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan: Memory-Centric Motion Estimator. VLSI Design 2005: 816-819

Marc Quax, Jos Huisken, Jef L. van Meerbergen: A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. DATE 2004: 230-235

Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen: An event-based network-on-chip monitoring service. HLDVT 2004: 149-154

Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Gerard Veldman, Jef L. van Meerbergen, Gerard de Haan: Streaming scratchpad memory organization for video applications. Circuits, Signals, and Systems 2004: 427-432

Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef L. van Meerbergen: Predictable Embedded Multiprocessor System Design. SCOPES 2004: 77-91

Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto: A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. VLSI Design 2004: 1083-

Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman: Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. CASES 2003: 63-72

Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355

Katarzyna Leijten-Nowak, Jef L. van Meerbergen: An FPGA architecture with enhanced datapath functionality. FPGA 2003: 195-204

Aleksandar Beric, Gerard de Haan, Jef L. van Meerbergen, Ramanathan Sethuraman: Towards an efficient high quality picture-rate up-converter. ICIP (2) 2003: 363-366

Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen: Networks on Silicon: Combining Best-Effort and Guaranteed Services. DATE 2002: 423-425

Katarzyna Leijten-Nowak, Jef L. van Meerbergen: Embedded Reconfigurable Logic Core for DSP Applications. FPL 2002: 89-101

John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf: Power-efficient layered turbo decoder processor. DATE 2001: 246-251

Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen: Phase coupled operation assignment for VLIW processors with distributed register files. ISSS 2001: 118-123

Sias Mostert, Nathalie Cossement, Rudy Lauwereins, Jef L. van Meerbergen: DF*: Modeling Dynamic Process Creation and Events for Interactive Multimedia Applications. IEEE International Workshop on Rapid System Prototyping 2001: 122-127

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: Prophid: A Platform-Based Design Method. Design Autom. for Emb. Sys. 6(1): 5-37 (2000)

Koen Van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5(4): 774-793 (2000)

Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen: Memory Arbitration and Cache Management in Stream-Based Systems. DATE 2000: 257-262

Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen: Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. FPL 2000: 695-706

Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint analysis for DSP code generation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 44-57 (1999)

Bernardo Kastrup, Jef L. van Meerbergen, Katarzyna Nowak: Seeking (the right) Problems for the Solutions of Reconfigurable Computing. FPL 1999: 520-525

Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen, Albert van der Werf: The Complexity of Multidimensional Periodic Scheduling. Discrete Applied Mathematics 89(1-3): 213-242 (1998)

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE 1998: 125-131

Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE 1998: 377-383

Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen: Multidimensional periodic scheduling: a solution approach. ED&TC 1997: 468-474

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC 1997: 611

Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess: PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD 1997: 164-169

Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess: Constraint Analysis for DSP Code Generation. ISSS 1997: 33-40

Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen, Albert van der Werf: Multidimensional Periodic Scheduling Model and Complexity. Euro-Par, Vol. II 1996: 226-235

Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Jef L. van Meerbergen, Albert van der Werf: Improved force-directed scheduling in high-throughput digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 945-960 (1995)

Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf: PHIDEO: High-level synthesis for high throughput applications. VLSI Signal Processing 9(1-2): 89-104 (1995)

Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess: Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC 1995: 593-598

Douglas M. Grant, Jef L. van Meerbergen, Paul E. R. Lippens: Optimization of Address Generator Hardware. EDAC-ETC-EUROASIC 1994: 325-329

Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten: Architectural strategies for high-throughput applications. VLSI Signal Processing 5(2-3): 201-220 (1993)

Jos Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, Jef L. van Meerbergen: Synthesis of synchronous communication hardware in a multiprocessor architecture. VLSI Signal Processing 6(3): 289-299 (1993)

Paul E. R. Lippens, Jef L. van Meerbergen, Wim F. J. Verhaegh, Albert van der Werf: Allocation of multiport memories for hierarchical data stream. ICCAD 1993: 728-735

Albert van der Werf, Emile H. L. Aarts, E. W. Heijnen, Jef L. van Meerbergen, Wim F. J. Verhaegh, Paul E. R. Lippens: A new method for retiming multi-functional processing units. VLSI 1993: 191-200

Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen: Efficiency improvements for force-directed scheduling. ICCAD 1992: 286-291

Albert van der Werf, M. J. H. Peek, Emile H. L. Aarts, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh: Area optimization of multi-functional processing units. ICCAD 1992: 292-299

Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh: Hierarchical Retiming Including Pipelining. VLSI 1991: 451-460

Jef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, J. Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man: An integrated automatic design system for complex DSP algorithms. VLSI Signal Processing 1(4): 265-278 (1990)

A. Delaruelle, O. McArdle, Jef L. van Meerbergen, C. Niessen: Synthesis of delay functions in DSP compilers. EURO-DAC 1990: 68-72

Dirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man: Open-ended system for high-level synthesis of flexible signal processors. EURO-DAC 1990: 272-276