Edison Mera

Manuel V. Hermenegildo, Francisco Bueno, Manuel Carro, Pedro López-García, Edison Mera, José F. Morales, Germán Puebla: An overview of Ciao and its design philosophy. TPLP 12(1-2): 219-252 (2012)

Edison Mera, Teresa Trigo, Pedro López-García, Manuel V. Hermenegildo: Profiling for Run-Time Checking of Computational Properties and Performance Debugging in Logic Programs. PADL 2011: 38-53

Manuel V. Hermenegildo, Francisco Bueno, Manuel Carro, Pedro López-García, Rémy Haemmerlé, Edison Mera, José F. Morales, Germán Puebla: An Overview of the Ciao System. RuleML Europe 2011: 2

Manuel V. Hermenegildo, Francisco Bueno, Manuel Carro, Pedro López-García, Edison Mera, José F. Morales, German Puebla: An overview of Ciao and its design philosophy. CoRR abs/1102.5497 (2011)

Edison Mera, Pedro López-García, Manuel V. Hermenegildo: Integrating Software Testing and Run-Time Checking in an Assertion Verification Framework. ICLP 2009: 281-295

Edison Mera, Pedro López-García, Manuel Carro, Manuel V. Hermenegildo: Towards execution time estimation in abstract machine-based languages. PPDP 2008: 174-184

Jorge A. Navas, Edison Mera, Pedro López-García, Manuel V. Hermenegildo: User-Definable Resource Bounds Analysis for Logic Programs. ICLP 2007: 348-363

Edison Mera, Pedro López-García, Germán Puebla, Manuel Carro, Manuel V. Hermenegildo: Combining Static Analysis and Profiling for Estimating Execution Times. PADL 2007: 140-154

Edison Mera, Pedro López-García, Germán Puebla, Manuel Carro, Manuel V. Hermenegildo: Towards Execution Time Estimation for Logic Programs via Static Analysis and Profiling. CoRR abs/cs/0701108 (2007)

Edison Mera, Pedro López-García, Germán Puebla, Manuel Carro, Manuel V. Hermenegildo: Using Combined Static Analysis and Profiling for Logic Program Execution Time Estimation. ICLP 2006: 431-432