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Eric Mercer
Eric G. Mercer
2010 – today
- 2012
[j8]Eric Mercer, Suzette Person, Neha Rungta: Computing and visualizing the impact of change with Java PathFinder extensions. ACM SIGSOFT Software Engineering Notes 37(6): 1-5 (2012)- [c23]Jun Shirako, Nick Vrvilo, Eric G. Mercer, Vivek Sarkar: Design, verification and applications of a new read-write lock algorithm. SPAA 2012: 48-57
- [c22]Everett Morse, Nick Vrvilo, Eric Mercer, Jay McCarthy: Modeling Asynchronous Message Passing for C Programs. VMCAI 2012: 332-347
- 2011
- [c21]Saint Wesonga, Eric G. Mercer, Neha Rungta: Guided test visualization: Making sense of errors in concurrent programs. ASE 2011: 624-627
- [c20]Topher Fischer, Eric Mercer, Neha Rungta: Symbolically modeling concurrent MCAPI executions. PPOPP 2011: 307-308
- 2010
- [c19]
2000 – 2009
- 2009
- [j7]Rahul Kumar, Eric G. Mercer, Annette Bunker: Improving Translation of Live Sequence Charts to Temporal Logic. Electr. Notes Theor. Comput. Sci. 250(1): 137-152 (2009)
- [j6]Rahul Kumar, Eric G. Mercer: Verifying Communication Protocols Using Live Sequence Chart Specifications. Electr. Notes Theor. Comput. Sci. 250(2): 33-48 (2009)
- [c18]Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer, Jim Holt: MCC: A runtime verification tool for MCAPI user applications. FMCAD 2009: 41-44
- [c17]Subodh Sharma, Ganesh Gopalakrishnan, Eric Mercer: Dynamic verification of Multicore Communication applications in MCAPI. HLDVT 2009: 100-105
- [c16]Neha Rungta, Eric G. Mercer: Clash of the Titans: tools and techniques for hunting bugs in concurrent programs. PADTAD 2009
- [c15]
- [c14]Neha Rungta, Eric G. Mercer, Willem Visser: Efficient Testing of Concurrent Programs with Abstraction-Guided Symbolic Execution. SPIN 2009: 174-191
- [e1]Ganesh Gopalakrishnan, Eitan Farchi, Eric Mercer (Eds.): Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, PADTAD 2009, Chicago, Illinois, USA, July 19-20, 2009. ACM 2009, ISBN 978-1-60558-655-7
- 2008
- [j5]Rahul Kumar, Eric G. Mercer: Improving Live Sequence Chart to Automata Transformation for Verification. ECEASST 10 (2008)
- [c13]Neha Rungta, Eric G. Mercer: A Meta Heuristic for Effectively Detecting Concurrency Errors. Haifa Verification Conference 2008: 23-37
- [c12]Daniel D. Walker, Eric G. Mercer, Kent E. Seamons: Or Best Offer: A Privacy Policy Negotiation Protocol. POLICY 2008: 173-180
- 2007
- [c11]Neha Rungta, Hyrum Carroll, Eric G. Mercer, Randall J. Roper, Mark J. Clement, Quinn Snell: Analyzing Gene Relationships for Down Syndrome with Labeled Transition Graphs. FMCAD 2007: 216-219
- [c10]Neha Rungta, Eric G. Mercer: Hardness for Explicit State Software Model Checking Benchmarks. SEFM 2007: 247-256
- [c9]Neha Rungta, Eric G. Mercer: Generating Counter-Examples Through Randomized Guided Search. SPIN 2007: 39-57
- [c8]
- 2006
- [c7]Neha Rungta, Eric G. Mercer: An Improved Distance Heuristic Function for Directed Software Model Checking. FMCAD 2006: 60-67
- 2005
- [j4]Rahul Kumar, Eric G. Mercer: Load Balancing Parallel Explicit State Model Checking. Electr. Notes Theor. Comput. Sci. 128(3): 19-34 (2005)
- [c6]Neha Rungta, Eric G. Mercer: A context-sensitive structural heuristic for guided search model checking. ASE 2005: 410-413
- [c5]Eric Mercer, Michael D. Jones: Model Checking Machine Code with the GNU Debugger. SPIN 2005: 251-265
- 2004
- [c4]
- 2003
- [j3]Michael D. Jones, Eric Mercer, Tonglaga Bao, Rahul Kumar, Peter Lamborn: Benchmarking Explicit State Parallel Model Checkers. Electr. Notes Theor. Comput. Sci. 89(1): 84-98 (2003)
- [j2]Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)
- 2002
- [j1]Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): 180-201 (2002)
- [c3]Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220
- 2001
- [c2]Kip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201
- [c1]Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193
Coauthor Index
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last updated on 2013-03-05 19:39 CET by the dblp team