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M. Ray Mercer
2000 – 2009
- 2005
[c54]Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer: An optimal test pattern selection method to improve the defect coverage. ITC 2005: 9- 2004
- [c53]Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer: Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. DATE 2004: 1066-1071
- [c52]Jennifer Dworak, James Wingfield, M. Ray Mercer: A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. DFT 2004: 460-468
- [c51]Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer: Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets. VTS 2004: 9-15
- 2003
- [c50]Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer: Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method. Asian Test Symposium 2003: 354-359
- [c49]James Wingfield, Jennifer Dworak, M. Ray Mercer: Function-Based Dynamic Compaction and its Impact on Test Set Sizes. DFT 2003: 167-174
- [c48]Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir: Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050
- 2002
- [c47]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC 2002: 371-374
- [c46]Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer: A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. DATE 2002: 94-99
- [c45]Rohit Kapur, Thomas W. Williams, M. Ray Mercer: Directed-Binary Search in Logic BIST Diagnostics. DATE 2002: 1121
- [c44]Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. DFT 2002: 177-185
- [c43]Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams: Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC 2002: 407-416
- 2001
- [j10]Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang: Defect-Oriented Testing and Defective-Part-Level Prediction. IEEE Design & Test of Computers 18(1): 31-41 (2001)
- 2000
- [c42]Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer: On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151-
- [c41]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D. ITC 2000: 930-939
1990 – 1999
- 1999
- [c40]Ronald W. Mehler, M. Ray Mercer: Multi-Level Logic Minimization through Fault Dictionary Analysis. ICCD 1999: 315-318
- [c39]Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer: Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies. ITC 1999: 1031-1037
- [c38]Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer: REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. VTS 1999: 268-274
- 1996
- [j9]Chanhee Oh, M. Ray Mercer: Efficient logic-level timing analysis using constraint-guided critical path search. IEEE Trans. VLSI Syst. 4(3): 346-355 (1996)
- [c37]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: A Better ATPG Algorithm and Its Design Principles. ICCD 1996: 248-253
- [c36]Jaehong Park, M. Ray Mercer: Using Functional Information and Strategy Switching in Sequential ATPG. ICCD 1996: 254-260
- [c35]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: Using Target Faults To Detect Non-Tartget Defects. ITC 1996: 629-638
- [c34]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly: IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792
- 1995
- [c33]Li-C. Wang, M. Ray Mercer, Thomas W. Williams: On Efficiently and Reliably Achieving Low Defective Part Levels. ITC 1995: 616-625
- [c32]Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams: On the decline of testing efficiency as fault coverage approaches 100%. VTS 1995: 74-83
- 1994
- [j8]Mark A. Heap, M. Ray Mercer: Least Upper Bounds an OBDD Sizes. IEEE Trans. Computers 43(6): 764-767 (1994)
- [c31]Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer: Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337
- [c30]Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams: Limitations in predicting defect level based on stuck-at fault coverage. VTS 1994: 186-191
- 1993
- [c29]
- [c28]Eun Sei Park, M. Ray Mercer: Switch-Level ATPG Using Constraint-Guided Line Justification. ITC 1993: 616-625
- 1992
- [j7]Eun Sei Park, M. Ray Mercer, Thomas W. Williams: The Total Delay Fault Model and Statistical Delay Fault Coverage. IEEE Trans. Computers 41(6): 688-698 (1992)
- [j6]Rohit Kapur, M. Ray Mercer: Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41(12): 1580-1588 (1992)
- [j5]Eun Sei Park, M. Ray Mercer: An efficient delay test generation system for combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(7): 926-938 (1992)
- [c27]M. Ray Mercer, Rohit Kapur, Don E. Ross: Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC 1992: 624-627
- [c26]Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage: ETA: electrical-level timing analysis. ICCAD 1992: 258-262
- [c25]Mark A. Heap, William A. Rogers, M. Ray Mercer: A Synthesis Algorithm for Two-Level XOR Based Circuits. ICCD 1992: 459-463
- [c24]Rohit Kapur, Jaehong Park, M. Ray Mercer: All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC 1992: 762-769
- 1991
- [j4]M. Ray Mercer: Testing and Design Verification of Electronic Components. IEEE Computer 24(9): 107-108 (1991)
- [j3]Don E. Ross, Kenneth M. Butler, M. Ray Mercer: Exact ordered binary decision diagram size when representing classes of symmetric functions. J. Electronic Testing 2(3): 243-259 (1991)
- [c23]Thomas W. Williams, Bill Underwood, M. Ray Mercer: The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. DAC 1991: 87-92
- [c22]Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer: Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC 1991: 417-420
- [c21]Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer: Delay Testing Quality in Timing-Optimized Designs. ITC 1991: 897-905
- 1990
- [j2]M. Ray Mercer: Guest Editorial: ITC 20th Anniversary. IEEE Design & Test of Computers 7(2): 2-3 (1990)
- [c20]Eun Sei Park, M. Ray Mercer: An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC 1990: 522-528
- [c19]Kenneth M. Butler, M. Ray Mercer: The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. DAC 1990: 673-678
1980 – 1989
- 1989
- [c18]C. Thomas Glover, M. Ray Mercer: A Deterministic Approach to Adjacency Testing for Delay Faults. DAC 1989: 351-356
- 1988
- [c17]
- [c16]Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler: CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. DAC 1988: 597-600
- [c15]Eun Sei Park, Thomas W. Williams, M. Ray Mercer: Statistical Delay Fault Coverage and Defect Level for Delay Faults. ITC 1988: 492-499
- [c14]Steven P. Smith, Bill Underwood, M. Ray Mercer: D^3FS: A Demand Driven Deductive Fault Simulator. ITC 1988: 582-592
- 1987
- [c13]
- [c12]
- 1986
- [j1]Ki Soo Hwang, M. Ray Mercer: Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 564-572 (1986)
- [c11]
- [c10]Ki Soo Hwang, M. Ray Mercer: Informed Test Generation Guidance Using Partially Specified Fanout Constraints. ITC 1986: 113-120
- [c9]
- [c8]Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood: Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. ITC 1986: 498-505
- [c7]
- 1985
- [c6]
- [c5]John Salick, Bill Underwood, M. Ray Mercer: Built-In Self Test Input Generator for Programmable Logic Arrays. ITC 1985: 115-125
- 1984
- [c4]
- 1983
- [c3]
- 1982
- [c2]
- 1981
- [c1]M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman: Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC 1981: 561-565
Coauthor Index
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last updated on 2012-12-02 20:34 CET by the dblp team