D. Michael Miller

Zahra Sasanian, D. Michael Miller: Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate Circuit. Multiple-Valued Logic and Soft Computing 18(1): 83-98 (2012)

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller: Synthesis of Semi-Classical Quantum Circuits. Multiple-Valued Logic and Soft Computing 18(1): 99-114 (2012)

D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. Multiple-Valued Logic and Soft Computing 19(1-3): 185-201 (2012)

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. Multiple-Valued Logic and Soft Computing 19(4): 361-378 (2012)

Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski: High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? Multiple-Valued Logic and Soft Computing 20(1-2): 89-120 (2012)

Zahra Sasanian, Robert Wille, D. Michael Miller: Realizing reversible circuits using a new class of quantum gates. DAC 2012: 36-41

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler: Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178

Zahra Sasanian, D. Michael Miller: Reversible and Quantum Circuit Optimization: A Functional Approach. RC 2012: 112-124

D. Michael Miller, Vincent C. Gaudet (Eds.): 42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012, Victoria, BC, Canada, May 14-16, 2012. IEEE 2012, isbn 978-1-4673-0908-0

Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller: Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL 2011: 131-138

D. Michael Miller, Robert Wille, Zahra Sasanian: Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates. ISMVL 2011: 288-293

Zahra Sasanian, D. Michael Miller: Transforming MCT Circuits to NCVW Circuits. RC 2011: 77-88

D. Michael Miller, Robert Wille, Rolf Drechsler: Reducing Reversible Circuit Cost by Adding Lines. ISMVL 2010: 217-222

Stanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic: Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups. ISMVL 2010: 307-312

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller: Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics. Multiple-Valued Logic and Soft Computing 15(4): 361-377 (2009)

D. Michael Miller, Robert Wille, Gerhard W. Dueck: Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756

D. Michael Miller, Radomir S. Stankovic: A Heterogeneous Decision Diagram Package. EUROCAST 2009: 540-547

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330

Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76

D. Michael Miller, Mitchell Aaron Thornton: Multiple Valued Logic - Concepts and Representations. Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers 2008, isbn 978-1-59829-190-2, pp. I-XIII, 1-135

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller: DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Transactions 91-A(12): 3793-3802 (2008)

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 436-444 (2008)

Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller: An efficient verification of quantum circuits under a practical restriction. CIT 2008: 873-879

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller: Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE 2008: 1378-1381

David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller: On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL 2008: 138-143

Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller: Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL 2008: 202-207

D. Michael Miller, Mitchell A. Thornton: Multiple Valued Logic: Concepts and Representations. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2007

Dmitri Maslov, D. Michael Miller: Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits. IET Computers & Digital Techniques 1(2): 98-104 (2007)

D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton: QMDD Minimization Using Sifting for Variable Reordering. Multiple-Valued Logic and Soft Computing 13(4-6): 537-552 (2007)

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007)

D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton: Variable Reordering and Sifting for QMDD. ISMVL 2007: 10

D. Michael Miller, Mitchell A. Thornton: QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL 2006: 30

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 807-817 (2005)

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6): 765-769 (2005)

Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck: Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213

D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov: A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80

Christine W. Chan, Witold Kinsner, Yingxu Wang, D. Michael Miller (Eds.): Proceedings of the 3rd IEEE International Conference on Cognitive Informatics (ICCI 2004), 16-17 August 2004, Victoria, Canada. IEEE Computer Society 2004, isbn 0-7695-2190-8

D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261

D. Michael Miller, Gerhard W. Dueck: On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240

D. Michael Miller, Rolf Drechsler: Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Simplification of Toffoli Networks via Templates. SBCCI 2003: 53-

Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183

Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend: Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL 2002: 123-129

D. Michael Miller, Rolf Drechsler: On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253

Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller: Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52

Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller: Spectral techniques in VLSI CAD. Kluwer 2001, isbn 978-0-7923-7433-6, pp. I-XIII, 1-250

Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio: TOP: An Algorithm for Three-Level Optimization of PLDs. DATE 2000: 751

Yasunori Nagata, D. Michael Miller, Masao Mukaidono: Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. ISMVL 2000: 402-

Yasunori Nagata, D. Michael Miller, Masao Mukaidono: B-ternary Logic Based Asynchronous Micropipeline. ISMVL 1999: 214-219

D. Michael Miller: An improved method for computing a generalized spectral coefficient. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 233-238 (1998)

Yasunori Nagata, D. Michael Miller, Masao Mukaidono: Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. ISMVL 1998: 38-

Shujian Zhang, D. Michael Miller, Jon C. Muzio: Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1588-1590 (1996)

Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller: A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ISMVL 1996: 92-97

D. Michael Miller, Noriaki Muranaka: Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. ISMVL 1996: 242-247

Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller: Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. J. Electronic Testing 7(3): 209-221 (1995)

Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller: Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. ISCAS 1994: 69-72

D. Michael Miller: Spectral Transformation of Multiple-Valued Decision Diagrams. ISMVL 1994: 89-96

D. Michael Miller: Multiple-Valued Logic Design Tools. ISMVL 1993: 2-11

Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller: Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. ISMVL 1993: 228-233

Shujian Zhang, Rod Byrne, D. Michael Miller: BIST Generators for Sequential Faults. ICCD 1992: 260-263

R. Tomczuk, D. Michael Miller: Autocorrelation Techniques for Multi-Bit Decoder PLAs. ISMVL 1992: 355-364

Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller: The analysis of one-dimensional linear cellular automata and their aliasing properties. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 767-778 (1990)

Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143

D. Michael Miller, Jon C. Muzio: Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. IEEE Trans. Computers 33(8): 765-769 (1984)

D. Michael Miller, Jon C. Muzio: Spectral Fault Signatures for Internally Unate Combinational Networks. IEEE Trans. Computers 32(11): 1058-1062 (1983)