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 | 2010 | |
|---|---|---|
| j3 |      | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang: Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation. IEEE Trans. VLSI Syst. 18(9): 1337-1347 (2010) |
| 2009 | ||
| j2 | | Omar Hafiz, Alexander V. Mitev, Janet Meiling Wang: A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty. IEICE Transactions 92-A(4): 1148-1160 (2009) |
| 2008 | ||
| j1 | | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang: Parameter reduction for variability analysis by slice inverse regression method. IET Circuits, Devices & Systems 2(1): 16-22 (2008) |
| c6 | | Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao: Finite-Point Gate Model for Fast Timing and Power Analysis. ISQED 2008: 657-662 |
| 2007 | ||
| c5 | | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang: Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method. ASP-DAC 2007: 468-473 |
| c4 | | Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang: Delay Uncertainty Reduction by Interconnect and Gate Splitting. ASP-DAC 2007: 690-695 |
| c3 | | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang: Principle Hessian direction based parameter reduction with process variation. ICCAD 2007: 632-637 |
| c2 | | Alexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang: A robust finite-point based gate model considering process variations. ICCAD 2007: 692-697 |
| c1 | | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang: Principle hessian direction based parameter reduction for interconnect networks with process variation. SLIP 2007: 41-46 |
| 1 | Vineet Agarwal | |
| 2 | Yu Cao | |
| 3 | Dinesh Ganesan | |
| 4 | Omar Hafiz | |
| 5 | Dongsheng Ma | |
| 6 | Michael M. Marefat | |
| 7 | Dheepan Shanmugasundaram | |
| 8 | Jin Sun | |
| 9 | Janet Meiling Wang (Janet Meiling Wang Roveda) |
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