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 | 2013 | |
|---|---|---|
| c8 |      | Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe: Development of low power many-core SoC for multimedia applications. DATE 2013: 773-777 |
| c7 | | Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto: A near-future prediction method for low power consumption on a many-core processor. DATE 2013: 1058-1059 |
| 2012 | ||
| c6 | | Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori: A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. ISSCC 2012: 222-223 |
| 2011 | ||
| j2 | | Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki: A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. J. Solid-State Circuits 46(1): 32-41 (2011) |
| 2010 | ||
| c5 | | Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki: A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC 2010: 326-327 |
| c4 | | Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John Stonick: Signal and power integrity for SoCs. ISSCC 2010: 520 |
| 2009 | ||
| j1 | | Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa: A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. IEEE Trans. VLSI Syst. 17(9): 1285-1296 (2009) |
| 2002 | ||
| c3 | | Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui: Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. ICCD 2002: 2-7 |
| 1998 | ||
| c2 | | Takashi Miyamori, Kunle Olukotun: A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. FCCM 1998: 2-11 |
| c1 | | Takashi Miyamori, Kunle Olukotun: REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). FPGA 1998: 261 |
Colors in the list of coauthors
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