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Takefumi Miyoshi
2010 – today
- 2012
[j7]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga: Design and Implementation of a Handshake Join Architecture on FPGA. IEICE Transactions 95-D(12): 2919-2927 (2012)- [j6]Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga: Using Cacheline Reuse Characteristics for Prefetcher Throttling. IEICE Transactions 95-D(12): 2928-2938 (2012)
- 2011
- [j5]Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. IEICE Transactions 94-D(12): 2319-2327 (2011)
- [j4]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. IJNC 1(2): 244-259 (2011)
- [c11]Takefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga: A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine. FPL 2011: 490-495
- [c10]Yasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga: An Implementation of Handshake Join on FPGA. ICNC 2011: 95-104
- [c9]Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga: CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. ICNC 2011: 127-133
- [c8]Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. ICNC 2011: 228-234
- 2010
- [c7]Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga: CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC 2010: 71-77
- [c6]Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise: Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC 2010: 133-139
- [c5]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga: An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161
- [c4]Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise: Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC 2010: 173-178
- [c3]Qin Wang, Junichi Ohmura, Shan Axida, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga: Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. ICNC 2010: 243-248
2000 – 2009
- 2009
- [c2]Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise: A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT 2009: 414-419
- [c1]Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe: Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. ReConFig 2009: 161-166
- 2007
- [j3]Takefumi Miyoshi, Nobuhiko Sugino: Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation. IEICE Transactions 90-D(12): 1967-1976 (2007)
- [j2]Takefumi Miyoshi, Nobuhiko Sugino: Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption. SIGARCH Computer Architecture News 35(5): 39-44 (2007)
- 2005
- [j1]Takefumi Miyoshi, Nobuhiko Sugino: Unified Phase Compiler by Use of 3-D Representation Space. IEICE Transactions 88-A(4): 838-845 (2005)
Coauthor Index
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last updated on 2013-01-09 14:37 CET by the dblp team