DBLP: Hiroyuki Mizuno

	2010
c7		Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno: Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6
c6		Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima: A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
	2009
c5		Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara: Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517
	2006
c4		Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno: Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295
	2001
c3		Kiyoo Itoh, Hiroyuki Mizuno: Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288
	1999
j1		Hiroyuki Mizuno, Koichiro Ishibashi: A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. VLSI Syst. 7(1): 139-144 (1999)
c2		Koichi Kise, Hiroyuki Mizuno, Masashi Yamaguchi, Keinosuke Matsumoto: On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents. ICDAR 1999: 301-304
	1998
c1		Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi: A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED 1998: 48-53

2010

Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno: Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima: A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101

2009

Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara: Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517

2006

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno: Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295

2001

Kiyoo Itoh, Hiroyuki Mizuno: Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288

1999

Hiroyuki Mizuno, Koichiro Ishibashi: A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. VLSI Syst. 7(1): 139-144 (1999)

Koichi Kise, Hiroyuki Mizuno, Masashi Yamaguchi, Keinosuke Matsumoto: On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents. ICDAR 1999: 301-304

1998

Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi: A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED 1998: 48-53

1	Tomohiro Akiyama	[c4]
2	Nobuto Arai	[c4]
3	Hiroyuki Asano	[c4]
4	Atsushi Hasegawa	[c6]
5	Toshihiro Hattori	[c4]
6	Izumi Hayashibara	[c4]
7	Motoki Higashida	[c4]
8	Kenji Hirose	[c4]
9	Tadashi Hoshi	[c4]
10	Naohiko Irie	[c4]
11	Takahiro Irita	[c4]
12	Koichiro Ishibashi	[j1] [c1]
13	Toshifumi Ishii	[c4]
14	Makoto Ishikawa	[c6]
15	Kiyoto Ito	[c7]
16	Masayuki Ito	[c6] [c5] [c4]
17	Kiyoo Itoh	[c3]
18	Yusuke Kanno	[c4]
19	Hironori Kasahara	[c6] [c5]
20	Hisashi Kato	[c4]
21	Keiji Kimura	[c6] [c5]
22	Koichi Kise	[c2]
23	Yoshikazu Kiyoshige	[c6]
24	Tomoyuki Kodama	[c7]
25	Takao Koike	[c4]
26	Hideo Maejima	[c6]
27	Masayoshi Mase	[c5]
28	S. Matsui	[c6]
29	Keinosuke Matsumoto	[c2]
30	Yujiro Miyairi	[c4]
31	Junichi Miyakoshi	[c6]
32	Masayuki Miyazaki	[c1]
33	Naozumi Morino	[c4]
34	Mitaro Namiki	[c5]
35	Osamu Nishii	[c6]
36	Kunihiko Nishiyama	[c4]
37	Yusuke Nitta	[c6]
38	Tohru Nojiri	[c6] [c5]
39	Koji Ohno	[c4]
40	Masafumi Onouchi	[c5]
41	Kenichi Osada	[c7]
42	Go Sado	[c4]
43	Makoto Saen	[c7]
44	Makoto Sato	[c5]
45	Mikiko Sato	[c5]
46	Masashi Satoh	[c6]
47	Yasuhisa Shimazaki	[c4]
48	Jun Shirako	[c5]
49	Masashi Takada	[c5]
50	Saneaki Tamaki	[c4]
51	Ken Tatezawa	[c4]
52	Koichi Terada	[c6]
53	Keisuke Toyama	[c5]
54	Reiko Tsuchihashi	[c4]
55	Yoshihiko Tsuchihashi	[c4]
56	Kunio Uchiyama	[c6]
57	Yasutaka Wada	[c6]
58	Hiroshi Yagi	[c4]
59	Tetsuhiro Yamada	[c4]
60	Tetsuya Yamada	[c6] [c4]
61	Masashi Yamaguchi	[c2]
62	Eiji Yamamoto	[c4]
63	Kazumasa Yanagisawa	[c4]
64	Yoshihiko Yasu	[c4]
65	Shinichi Yoshioka	[c4]
66	Yoichi Yuyama	[c6]

Hiroyuki Mizuno

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