Masayuki Mizuno

Ken'ichiro Hijioka, Masaharu Matsudaira, Koichi Yamaguchi, Masayuki Mizuno: A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. ISSCC 2013: 406-407

Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno: A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. J. Solid-State Circuits 47(2): 435-443 (2012)

Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno: A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. J. Solid-State Circuits 47(4): 832-840 (2012)

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno: A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Transactions 94-C(1): 102-109 (2011)

Koichi Yamaguchi, Masayuki Mizuno: Dicode Partial Response Signaling over Inductively-Coupled Channel. IEICE Transactions 94-C(4): 613-618 (2011)

Koichi Yamaguchi, Masayuki Mizuno: A Duobinary Signaling for Asymmetric Multi-Chip Communication. IEICE Transactions 94-C(4): 619-626 (2011)

Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno: A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. J. Solid-State Circuits 45(1): 15-22 (2010)

Haruya Ishizaki, Masayuki Mizuno: A 0.2 mm ² , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability. J. Solid-State Circuits 45(4): 921-927 (2010)

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda: An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. J. Solid-State Circuits 45(10): 2057-2065 (2010)

Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda: A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. CICC 2010: 1-4

Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno: A 16Gb/s 1^st-Tap FFE and 3-Tap DFE in 90nm CMOS. ISSCC 2010: 162-163

Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno: A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC 2010: 192-193

Masahiro Sekimoto, Sadao Kawamura, Tomoya Ishitsubo, Shinsuke Akizuki, Masayuki Mizuno: Basis-motion torque composition approach: generation of feedforward inputs for control of multi-joint robots. IROS 2009: 3127-3132

Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno: A chip-stacked memory for on-chip SRAM-rich SoCs and processors. ISSCC 2009: 60-61

Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama: A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. ISSCC 2009: 192-193

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno: Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471

Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi: LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Transactions 91-C(2): 131-137 (2008)

Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda: Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Transactions 90-C(4): 829-835 (2007)

Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kozuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono: Solid-Electrolyte Nanometer Switch. IEICE Transactions 89-C(11): 1492-1498 (2006)