Paul Molitor

André Gießler, Jörg Ritter, Paul Molitor: Model Checking for PLC based Railway Interlocking Systems. MBMV 2013: 71-82

Paul Molitor: Reviewer Thanks. it - Information Technology 53(1): 44- (2011)

André Gießler, Jörg Ritter, Paul Molitor: BDD-based Analysis of Test Cases for PLC-based Railway Interlocking Systems. MBMV 2011: 133-143

Christian Ernst, Changxing Dong, Gerold Jäger, Dirk Richter, Paul Molitor: Finding Good Tours for Huge Euclidean TSP Instances by Iterative Backbone Contraction. AAIM 2010: 119-130

Changxing Dong, Gerold Jäger, Dirk Richter, Paul Molitor: Effective Tour Searching for TSP by Contraction of Pseudo Backbone Edges. AAIM 2009: 175-187

Changxing Dong, Christian Ernst, Gerold Jäger, Dirk Richter, Paul Molitor: Effective Heuristics for Large Euclidean TSP Instances Based on Pseudo Backbones. CTW 2009: 3-6

Bernd Becker, Paul Molitor: Technische Informatik - eine einführende Darstellung. Oldenbourg 2008, isbn 978-3-486-58650-3, pp. I-XVI, 1-419

Paul Molitor: Gutachter 2008. it - Information Technology 50(6): 410 (2008)

Gerold Jäger, Paul Molitor: Algorithms and Experimental Study for the Traveling Salesman Problem of Second Order. COCOA 2008: 211-224

Dirk Richter, Boris Goldengorin, Gerold Jäger, Paul Molitor: Improving the Efficiency of Helsgaun's Lin-Kernighan Heuristic for the Symmetric TSP. CAAN 2007: 99-111

Changxing Dong, Paul Molitor: What Graphs can be Efficiently Represented by BDDs? ICCTA 2007: 128-134

Paul Molitor: ...was wird mit übrigens? it - Information Technology 48(4): 247 (2006)

Boris Goldengorin, Gerold Jäger, Paul Molitor: Some Basics on Tolerances. AAIM 2006: 194-206

Boris Goldengorin, Gerold Jäger, Paul Molitor: Tolerance Based Contract-or-Patch Heuristic for the Asymmetric TSP. CAAN 2006: 86-97

Paul Molitor: Gutachter 2005. it - Information Technology 47(6): 366- (2005)

Paul Molitor, Jörg Ritter: VHDL - eine Einführung. Pearson Studium 2004, isbn 978-3-8273-7047-1, pp. 1-287

Paul Molitor: Gutachter 2004. it - Information Technology 46(6): 360- (2004)

Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor: Polynomial Formal Verification of Multipliers. Formal Methods in System Design 22(1): 39-58 (2003)

Heinz Zemanek, Johannes Oldenbourg, Paul Molitor, Klaus Küspert, Kurt Rothermel: Zum neuen Jahrgang. it - Information Technology 45(1): 3-5 (2003)

Janett Mohnke, Paul Molitor, Sharad Malik: Limits of Using Signatures for Permutation Independent Boolean Comparison. Formal Methods in System Design 21(2): 167-191 (2002)

Robby Schönfeld, Paul Molitor: What are the samples for learning efficient routing heuristics? [MCM routing]. APCCAS (1) 2002: 267-272

Janett Mohnke, Paul Molitor, Sharad Malik: Application of BDDs in Boolean matching techniques for formal logic combinational verification. STTT 3(2): 207-216 (2001)

Jörg Ritter, Paul Molitor: A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. FPGA 2001: 201-206

Laura Heinrich-Litan, Paul Molitor: Least Upper Bounds for the Size of OBDDs Using Symmetry Properties. IEEE Trans. Computers 49(4): 360-368 (2000)

Riccardo Forth, Paul Molitor: An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines. ASP-DAC 2000: 61-66

Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor: k-Layer Straightline Crossing Minimization by Speeding Up Sifting. Graph Drawing 2000: 253-258

Sandro Wefel, Paul Molitor: Prove that a faulty multiplier is faulty!? ACM Great Lakes Symposium on VLSI 2000: 43-46

Riccardo Forth, Paul Molitor: Permutation Independent Comparison of Pseudo Boolean Functions. MBMV 2000: 79-88

Paul Molitor, Christoph Scholl: Datenstrukturen und effiziente Algorithmen für die Logiksynthese kombinatorischer Schaltungen. Teubner 1999, isbn 978-3-519-02945-8, pp. 1-298

Janett Mohnke, Paul Molitor, Sharad Malik: Establishing latch correspondence for sequential circuits using distinguishing signatures. Integration 27(1): 33-46 (1999)

Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler: BDD minimization using symmetries. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 81-100 (1999)

Christian Matuszewski, Robby Schönfeld, Paul Molitor: Using Sifting for k -Layer Straightline Crossing Minimization. Graph Drawing 1999: 217-224

Laura Heinrich-Litan, Ursula Fissgus, St. Sutter, Paul Molitor, Thomas Rauber: Modeling the Communication Behavior of Distributed Memory Machines by Genetic Programming. Euro-Par 1998: 273-278

Christoph Scholl, S. Melchior, Günter Hotz, Paul Molitor: Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries. ED&TC 1997: 229-234

Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor: Polynomial Formal Verification of Multipliers. VTS 1997: 150-157

Laura Heinrich-Litan, Paul Molitor, Dirk Möller: Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs. Great Lakes Symposium on VLSI 1996: 126-

Tolga Asveren, Paul Molitor: New Crossover Methods For Sequencing Problems. PPSN 1996: 290-299

Bernd Becker, Rolf Drechsler, Paul Molitor: On the generation of area-time optimal testable adders. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995)

Janett Mohnke, Paul Molitor, Sharad Malik: Limits of using signatures for permutation independent Boolean comparison. ASP-DAC 1995

Christoph Scholl, Paul Molitor: Communication based FPGA synthesis for multi-output Boolean functions. ASP-DAC 1995

Ines Peters, Paul Molitor: Priority driven channel pin assignment. Great Lakes Symposium on VLSI 1995: 132-

Paul Molitor, Uwe Sparmann, Dorothea Wagner: Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated. VLSI Design 1994: 149-154

Michael Kaufmann, Paul Molitor, Wolfgang Vogelgesang: Performance Driven k-Layer Wiring. STACS 1992: 489-500

Paul Molitor: A Survey on Wiring. Elektronische Informationsverarbeitung und Kybernetik 27(1): 3-19 (1991)

Paul Molitor: Constrained via minimization for systolic arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 537-542 (1990)

Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann: A graphical system for hierarchical specifications and checkups of VLSI circuits. EURO-DAC 1990: 174-179

Reiner Kolla, Paul Molitor, Hans-Georg Osthof: Einführung in den VLSI-Entwurf. Leitfäden und Monographien der Informatik, Teubner 1989, isbn 978-3-519-02273-2, pp. 1-352

Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof: Hierarchical Design Based on a Calculus of Nets. DAC 1987: 649-653

Paul Molitor: On the Contact-Minimization-Problem. STACS 1987: 420-431

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. Inform., Forsch. Entwickl. 1(1): 38-47 (1986)

Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor: Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. Inform., Forsch. Entwickl. 1(2): 72-82 (1986)

Günter Hotz, Reiner Kolla, Paul Molitor: On Network Algebras and Recursive Equations. Graph-Grammars and Their Application to Computer Science 1986: 250-261