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Jaime H. Moreno
Author information
- IBM
2010 – today
- 2010
[c11]Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun: Extreme scale computing: Challenges and opportunities. HPCA 2010: 1- [c10]Josep Torrellas, Bill Gropp, Jaime H. Moreno, Kunle Olukotun, Vivek Sarkar: Extreme scale computing: challenges and opportunities. PPOPP 2010: 101-102
2000 – 2009
- 2009
- [c9]John P. Karidis, José E. Moreira, Jaime H. Moreno: True value: assessing and optimizing the cost of computing at the data center level. Conf. Computing Frontiers 2009: 185-192
- 2006
- [c8]Jaime H. Moreno: Chip-level integration: the new frontier for microprocessor architecture. SPAA 2006: 328
- 2004
- [c7]Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno: Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452
- 2003
- [j5]Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter: An innovative low-power high-performance programmable signal processor for digital communications. IBM Journal of Research and Development 47(2-3): 299-326 (2003)
- [c6]Hillery C. Hunter, Jaime H. Moreno: A new look at exploiting data parallelism in embedded systems. CASES 2003: 159-169
- [c5]Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno: Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
- [e1]Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi (Eds.): Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003. ACM 2003, ISBN 1-58113-676-5
1990 – 1999
- 1999
- [c4]Mayan Moudgill, P. Bose, Jaime H. Moreno: Validation of Turandot, a fast processor model for microarchitecture exploration. IPCCC 1999: 451-457
- 1997
- [j4]Jaime H. Moreno, Mayan Moudgill, Kemal Ebcioglu, Erik R. Altman, C. Brian Hall, Rene Miranda, Shyh-Kwei Chen, Arkady Polyak: Simulation/evaluation environment for a VLIW processor architecture. IBM Journal of Research and Development 41(3): 287-302 (1997)
- [c3]Jaime H. Moreno, Mayan Moudgill: Scalable Instruction-Level Parallelism Through Tree-Instructions. International Conference on Supercomputing 1997: 1-11
- 1993
- [j3]
- 1991
- [j2]Jaime H. Moreno, Miguel E. Figueroa, Tomás Lang: Linear pseudosystolic array for partitioned matrix algorithms. VLSI Signal Processing 3(3): 201-214 (1991)
- 1990
- [j1]Jaime H. Moreno, Tomás Lang: Matrix Computations on Systolic-Type Meshes. IEEE Computer 23(4): 32-51 (1990)
1980 – 1989
- 1988
- [c2]Jaime H. Moreno, Tomás Lang: Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure. ICPP (1) 1988: 28-31
- 1986
- [c1]Jaime H. Moreno, Tomás Lang: Replication and Pipelining in Multiple-Instance Algorithms. ICPP 1986: 285-292
Coauthor Index
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last updated on 2012-12-11 20:08 CET by the dblp team