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Hiroki Morimura
2010 – today
- 2010
[j4]Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida: Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. J. Solid-State Circuits 45(5): 1080-1087 (2010)- [c4]Toshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh: Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. ISSCC 2010: 504-505
2000 – 2009
- 2007
- [j3]Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi: Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Transactions 90-C(10): 1892-1899 (2007)
- 2006
- [j2]Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi: Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Transactions 89-C(4): 540-550 (2006)
- 2005
- [j1]Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi: Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Transactions 88-C(5): 1070-1078 (2005)
- 2002
- [c3]Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi: A Fingerprint Verification Algorithm Using the Differential Matching Rate. ICPR (3) 2002: 799-802
1990 – 1999
- 1999
- [c2]Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka: A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. ISLPED 1999: 12-17
- 1996
- [c1]
Coauthor Index
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last updated on 2012-12-02 21:37 CET by the dblp team