Nilanjan Mukherjee

other persons with the same name:

• Nilanjan Mukherjee 0002

	2012
j16		Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: EDT Bandwidth Management in SoC Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1894-1907 (2012)
c42		Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: Low power programmable PRPG with enhanced fault coverage gradient. ITC 2012: 1-9
	2011
j15		Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer: Ring Generator: An Ultimate Linear Feedback Shift Register. IEEE Computer 44(6): 64-71 (2011)
j14		Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1072-1085 (2011)
j13		Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer: Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1225-1238 (2011)
c41		Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek: Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium 2011: 419-424
c40		Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer: Power Aware Embedded Test. Asian Test Symposium 2011: 511-516
c39		Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Reduced ATE Interface for High Test Data Compression. European Test Symposium 2011: 99-104
c38		Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9
	2010
j12		Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 117-126 (2010)
j11		Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 441-453 (2010)
c37		Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer: Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274
c36		Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer: Low power compression of incompatible test cubes. ITC 2010: 704-713
c35		Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab: Low capture power at-speed test in EDT environment. ITC 2010: 714-723
	2009
c34		Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer: Compression based on deterministic vector clustering of incompatible test cubes. ITC 2009: 1-10
c33		Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: Fault diagnosis for embedded read-only memories. ITC 2009: 1-10
c32		Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design 2009: 23-25
c31		Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design 2009: 275-280
c30		Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer: Highly X-Tolerant Selective Compaction of Test Responses. VTS 2009: 245-250
	2008
j10		Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)
c29		Nilanjan Mukherjee: Targeting "Zero DPPM" - Can we ever get there? DFT 2008: 163-163
c28		Kirk Beatty, Nilanjan Mukherjee: Flattening 3D Triangulations for Quality Surface Mesh Generation. IMR 2008: 125-139
c27		Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, D. Sartoretti: High Test Quality in Low Pin Count Applications. ITC 2008: 1
c26		Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC 2008: 1-10
	2007
j9		Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
	2006
j8		Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: High Performance Dense Ring Generators. IEEE Trans. Computers 55(1): 83-87 (2006)
c25		Nilanjan Mukherjee: High Quality Bi-Linear Transfinite Meshing with Interior Point Constraints. IMR 2006: 309-323
c24		Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10
	2005
c23		Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press: Achieving High Test Quality with Reduced Pin Count Testing. Asian Test Symposium 2005: 312-317
c22		Nilanjan Mukherjee: Improving Test Quality Using Test Data Compression. Asian Test Symposium 2005: 463
c21		Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy: Full-speed field-programmable memory BIST architecture. ITC 2005: 9
c20		Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee: Chasing subtle embedded RAM defects for nanometer technologies. ITC 2005: 9
	2004
j7		Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee: Embedded deterministic test. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004)
c19		Nilanjan Mukherjee: Cost of Test - Taking Control. ITC 2004: 1431
c18		Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht: Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23
c17		Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900
c16		Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Planar High Performance Ring Generators. VTS 2004: 193-198
	2003
j6		Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Design & Test of Computers 20(5): 58-66 (2003)
c15		Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104
c14		Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski: Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220
	2002
j5		Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)
j4		Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)
c13		Nilanjan Mukherjee: A Hybrid, Variational 3D Smoother For Orphaned Shell Meshes. IMR 2002: 379-390
c12		Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82
c11		Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
c10		Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516
	2001
j3		Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Testing Schemes for FIR Filter Structures. IEEE Trans. Computers 50(7): 674-688 (2001)
c9		Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-
c8		Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy: On RTL scan design. ITC 2001: 728-737
	1998
j2		Nilanjan Mukherjee, Ramesh Karri: Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. J. Electronic Testing 13(2): 189-200 (1998)
c7		Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik: A BIST scheme for the detection of path-delay faults. ITC 1998: 422-431
c6		Ramesh Karri, Nilanjan Mukherjee: Versatile BIST: an integrated approach to on-line/off-line BIST. ITC 1998: 910-917
	1997
j1		Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers 46(7): 795-810 (1997)
c5		Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Parameterizable Testing Scheme for FIR Filters. ITC 1997: 694-703
	1995
c4		Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338
c3		Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On testable multipliers for fixed-width data path architectures. ICCAD 1995: 541-547
c2		Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer: Arithmetic built-in self test for high-level synthesis. VTS 1995: 132-139
	1993
c1		Thomas Charles Wilson, Nilanjan Mukherjee, M. K. Garg, Dilip K. Banerji: An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197

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