- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| j3 |      | Christian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore: Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors. IEEE Trans. Computers 62(5): 914-928 (2013) |
| 2009 | ||
| j2 | | Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit: An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE Trans. VLSI Syst. 17(3): 319-329 (2009) |
| 2008 | ||
| c11 | | Rosemary M. Francis, Simon W. Moore, Robert D. Mullins: A Network of Time-Division Multiplexed Wiring for FPGAs. NOCS 2008: 35-44 |
| 2007 | ||
| c10 | | Robert D. Mullins, Simon W. Moore: Demystifying Data-Driven and Pausible Clocking Schemes. ASYNC 2007: 175-185 |
| c9 | | Arnab Banerjee, Robert D. Mullins, Simon W. Moore: A Power and Energy Exploration of Network-on-Chip Architectures. NOCS 2007: 163-172 |
| 2006 | ||
| c8 | | Robert D. Mullins, Andrew West, Simon W. Moore: The design and implementation of a low-latency on-chip network. ASP-DAC 2006: 164-169 |
| 2004 | ||
| c7 | | Robert D. Mullins, Andrew West, Simon W. Moore: Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA 2004: 188-197 |
| 2003 | ||
| j1 | | Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier: Balanced self-checking asynchronous logic for smart card applications. Microprocessors and Microsystems 27(9): 421-430 (2003) |
| c6 | | Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor: Security Evaluation of Asynchronous Circuits. CHES 2003: 137-151 |
| 2002 | ||
| c5 | | George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson: Point to Point GALS Interconnect. ASYNC 2002: 69-75 |
| c4 | | Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor: Improving Smart Card Security Using Self-Timed Circuits. ASYNC 2002: 211-218 |
| 2000 | ||
| c3 | | Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson: Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD 2000: 73- |
| 1999 | ||
| c2 | | D. K. Arvind, Robert D. Mullins: A Fully Asynchronous Superscalar Architecture. IEEE PACT 1999: 17-22 |
| 1995 | ||
| c1 | | D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello: Micronets: a model for decentralising control in asynchronous processor architectures. ASYNC 1995: 190-199 |
Colors in the list of coauthors
Last update Sat May 25 08:47:59 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page