Naveen Muralimanohar

Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez: Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro 32(3): 79-87 (2012)

Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn: Optical High Radix Switch Design. IEEE Micro 32(3): 100-109 (2012)

Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi: CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE 2012: 33-38

Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi: Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA 2012: 41-52

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas: CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD 2012: 294-301

Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan: BOOM: Enabling mobile memory based low-power server DIMMs. ISCA 2012: 25-36

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi: LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA 2012: 285-296

Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie: Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214

Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar: Multi-Core Cache Hierarchies. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011

Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi: Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. TACO 8(2): 6 (2011)

Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez: FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA 2011: 466-477

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi: Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA 2011: 425-436

Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn: The role of optics in future high radix switch design. ISCA 2011: 437-448

Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi: System implications of memory reliability in exascale computing. SC 2011: 46

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian: Towards scalable, energy-efficient, bus-based on-chip networks. HPCA 2010: 1-12

Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi: Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA 2010: 175-186

Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi: Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian: Non-uniform power access in large caches with low-swing wires. HiPC 2009: 59-68

Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell: Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274

Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie: Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009

Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008)

Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian: Scalable and reliable communication for hardware transactional memory. PACT 2008: 144-154

Naveen Muralimanohar, Rajeev Balasubramonian: Interconnect design considerations for large NUCA caches. ISCA 2007: 369-380

Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14

Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter: Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26(6): 40-52 (2006)

Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter: Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA 2006: 339-351

Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian: Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: 100-111

Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA 2005: 28-39