Saburo Muroga

Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga: Design of logic circuits with wired-logic utilizing transduction method. Systems and Computers in Japan 27(11): 19-28 (1996)

Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga: Optimization methods for look-up table-type FPGAs based on permissible functions. Systems and Computers in Japan 27(12): 92-101 (1996)

Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga: Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC 1995

Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga: A Shared Memory Parallel Algorithm for Logic Synthesis. VLSI Design 1993: 317-322

Saburo Muroga: Computer-Aided Logic Synthesis for VLSI Chips. Advances in Computers 32: 1-103 (1991)

Sung Je Hong, Saburo Muroga: Absolute Minimization of Completely Specified Switching Functions. IEEE Trans. Computers 40(1): 53-65 (1991)

Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita: A Resynthesis Approach for Network Optimization. DAC 1991: 458-463

Johnson Chan Limqueco, Saburo Muroga: Logic Optimization of MOS Networks. DAC 1991: 464-469

Kuang-Chien Chen, Saburo Muroga: Timing Optimization for Multi-Level Combinational Networks. DAC 1990: 339-344

Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney: The Transduction Method-Design of Logic Networks Based on Permissible Functions. IEEE Trans. Computers 38(10): 1404-1424 (1989)

Hung Chi Lai, Saburo Muroga: Design of MOS networks in single-rail input logic for incompletely specified functions. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 339-345 (1988)

Hung Chi Lai, Saburo Muroga: Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. IEEE Trans. Computers 36(2): 157-166 (1987)

Robert Brian Cutler, Saburo Muroga: Derivation of Minimal Sums for Completely Specified Functions. IEEE Trans. Computers 36(3): 277-292 (1987)

Yahiko Kambayashi, Saburo Muroga: Properties of Wired Logic. IEEE Trans. Computers 35(6): 550-563 (1986)

Ming Huei Young, Saburo Muroga: Minimal covering problem and PLA minimization. International Journal of Parallel Programming 14(6): 337-364 (1985)

Ming Huei Young, Saburo Muroga: Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. IEEE Trans. Computers 34(6): 523-541 (1985)

Ging-Shung Yu, Saburo Muroga: Parallel multipliers with NOR gates based on G-minimum adders. International Journal of Parallel Programming 13(2): 111-121 (1984)

Akito Sakurai, Saburo Muroga: Parallel Binary Adders with a Minimum Number of Connections. IEEE Trans. Computers 32(10): 969-976 (1983)

Hung Chi Lai, Saburo Muroga: Logic Networks of Carry-Save Adders. IEEE Trans. Computers 31(9): 870-882 (1982)

Robert Brian Cutler, Saburo Muroga: Useless prime implicants of incompletely specified multiple-output switching functions. International Journal of Parallel Programming 9(4): 337-350 (1980)

Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga: Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. IEEE Trans. Computers 28(1): 76-85 (1979)

Robert Brian Cutler, Saburo Muroga: Comments on ``Generalization of Consensus Theory and Application to the Minimization of Boolean Functions''. IEEE Trans. Computers 28(7): 542-543 (1979)

Hung Chi Lai, Saburo Muroga: Minimum Parallel Binary Adders with NOR (NAND) Gates. IEEE Trans. Computers 28(9): 648-659 (1979)

Robert Brian Cutler, Saburo Muroga: Comments on ``Computing Irredundant Normal Forms from Abbreviated Presence Functions''. IEEE Trans. Computers 28(11): 874-875 (1979)

Saburo Muroga, Hung Chi Lai: Minimization of Logic Networks Under a Generalized Cost Function. IEEE Trans. Computers 25(9): 893-907 (1976)

Hung Chi Lai, Tomoyasu Nakagawa, Saburo Muroga: Redundancy check technique for designing optimal networks by branch-and-bound method. International Journal of Parallel Programming 3(3): 251-271 (1974)

Toshihide Ibaraki, T. K. Liu, C. R. Baugh, Saburo Muroga: An implicit enumeration program for zero-one integer programming. International Journal of Parallel Programming 1(1): 75-92 (1972)

Saburo Muroga: Threshold logic and its applications. Wiley 1971, isbn 978-0-471-62530-8, pp. I-XIV, 1-478

Toshihide Ibaraki, Saburo Muroga: Adaptive Linear Classifier by Linear Programming. IEEE Trans. Systems Science and Cybernetics 6(1): 53-62 (1970)

Saburo Muroga: Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight. SWCT (FOCS) 1962: 169-184

Saburo Muroga: Functional forms of majority functions and a necessary and sufficient condition for their realizability. SWCT (FOCS) 1961: 39-46

Calvin C. Elgot, Saburo Muroga: Two problems on threshold functions. SWCT (FOCS) 1961: 166

Saburo Muroga: The principle of majority decision logical elements and the complexity of their circuits. IFIP Congress 1959: 400-406