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Brian T. Murray
2000 – 2009
- 2005
[j11]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Dependable communication synthesis for distributed embedded systems. Rel. Eng. & Sys. Safety 89(1): 81-92 (2005)- [j10]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. IEEE Trans. Parallel Distrib. Syst. 16(3): 258-270 (2005)
- 2003
- [c10]Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray: Low-Cost On-Line Fault Detection Using Control Flow Assertions. IOLTS 2003: 137-143
- [c9]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Dependable Communication Synthesis for Distributed Embedded Systems. SAFECOMP 2003: 275-288
- 2002
- [c8]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Time-Constrained Failure Diagnosis in Distributed Embedded Systems. DSN 2002: 449-458
- 2000
- [j9]Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. IEEE Trans. VLSI Syst. 8(5): 633-636 (2000)
1990 – 1999
- 1999
- [j8]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Deterministic Built-in Pattern Generation for Sequential Circuits. J. Electronic Testing 15(1-2): 97-114 (1999)
- [c7]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray: Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. SRDS 1999: 212-221
- [c6]Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar: Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. VTS 1999: 22-27
- 1998
- [j7]Hussain Al-Asaad, Brian T. Murray, John P. Hayes: Online BIST for Embedded Systems. IEEE Design & Test of Computers 15(4): 17-24 (1998)
- [j6]Hussain Al-Asaad, John P. Hayes, Brian T. Murray: Scalable Test Generators for High-Speed Datapath Circuits. J. Electronic Testing 12(1-2): 111-125 (1998)
- [j5]Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes: Optimal Zero-Aliasing Space Compaction of Test Responses. IEEE Trans. Computers 47(11): 1171-1187 (1998)
- [j4]Krishnendu Chakrabarty, Brian T. Murray: Design of built-in test generator circuits using width compression. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1044-1051 (1998)
- [c5]Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray: Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. VTS 1998: 418-423
- 1997
- [c4]Krishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray: Test Width Compression for Built-In Self Testing. ITC 1997: 328-337
- 1996
- [j3]Brian T. Murray, John P. Hayes: Testing ICs: Getting to the Core of the Problem. IEEE Computer 29(11): 32-38 (1996)
- 1995
- [c3]Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes: Optimal Space Compaction of Test Responses. ITC 1995: 834-843
- 1991
- [c2]
- 1990
- [j2]Brian T. Murray, John P. Hayes: Hierarchical test generation using precomputed tests for modules. IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 594-603 (1990)
1980 – 1989
- 1989
- [j1]Debashis Bhattacharya, Brian T. Murray, John P. Hayes: High-Level Test Generation for VLSI. IEEE Computer 22(4): 16-24 (1989)
- 1988
- [c1]Brian T. Murray, John P. Hayes: Hierarchical Test Generation Using Precomputed Tests for Modules. ITC 1988: 221-229
Coauthor Index
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last updated on 2012-12-02 21:11 CET by the dblp team