- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| c71 |      | Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, Chita R. Das: OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance. ASPLOS 2013: 395-406 |
| c70 | | Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai: Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. DATE 2013: 1285-1290 |
| 2012 | ||
| j25 | | Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, Parthasarathy Ranganathan: Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management. Computer Architecture Letters 11(2): 61-64 (2012) |
| j24 | | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu: A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips. IEEE Micro 32(3): 17-25 (2012) |
| j23 | | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt: Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems. ACM Trans. Comput. Syst. 30(2): 7 (2012) |
| c69 | | Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Todd C. Mowry: The evicted-address filter: a unified mechanism to address both cache pollution and thrashing. PACT 2012: 355-366 |
| c68 | | Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry: Base-delta-immediate compression: practical data compression for on-chip caches. PACT 2012: 377-388 |
| c67 | | Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das: Application-aware prefetch prioritization in on-chip networks. PACT 2012: 441-442 |
| c66 | | Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi: Application-to-core mapping policies to reduce memory interference in multi-core systems. PACT 2012: 455-456 |
| c65 | | Gennady Pekhimenko, Todd C. Mowry, Onur Mutlu: Linearly compressed pages: a main memory compression framework with low complexity and low latency. PACT 2012: 489-490 |
| c64 | | José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt: Bottleneck identification and scheduling in multithreaded applications. ASPLOS 2012: 223-234 |
| c63 | | Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai: Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE 2012: 521-526 |
| c62 | | Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai: Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. ICCD 2012: 94-101 |
| c61 | | HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu: Row buffer locality aware caching policies for hybrid memories. ICCD 2012: 337-344 |
| c60 | | Justin Meza, Jing Li, Onur Mutlu: A case for small row buffers in non-volatile main memories. ICCD 2012: 484-485 |
| c59 | | Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu: RAIDR: Retention-aware intelligent DRAM refresh. ISCA 2012: 1-12 |
| c58 | | Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu: A case for exploiting subarray-level parallelism (SALP) in DRAM. ISCA 2012: 368-379 |
| c57 | | Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu: Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. ISCA 2012: 416-427 |
| c56 | | Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu: HAT: Heterogeneous Adaptive Throttling for On-Chip Networks. SBAC-PAD 2012: 9-18 |
| c55 | | George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, Srinivasan Seshan: On-chip networks from a networking perspective: congestion and scalability in many-core interconnects. SIGCOMM 2012: 407-418 |
| e2 | | Lixin Zhang, Onur Mutlu (Eds.): Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, Beijing, China, June 16, 2012. ACM 2012, isbn 978-1-4503-1219-6 |
| 2011 | ||
| j22 | | |
| j21 | | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. IEEE Micro 31(1): 29-41 (2011) |
| j20 | | M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt: Data Marshaling for Multicore Systems. IEEE Micro 31(1): 56-64 (2011) |
| j19 | | Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter: Thread Cluster Memory Scheduling. IEEE Micro 31(1): 78-89 (2011) |
| j18 | | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt: Prefetch-Aware Memory Controllers. IEEE Trans. Computers 60(10): 1406-1430 (2011) |
| c54 | | Chris Fallin, Chris Craik, Onur Mutlu: CHIPPER: A low-complexity bufferless deflection router. HPCA 2011: 144-155 |
| c53 | | Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, Onur Mutlu: Memory power management via dynamic voltage/frequency scaling. ICAC 2011: 31-40 |
| c52 | | Licheng Chen, Yongbing Huang, Yungang Bao, Onur Mutlu, Guangming Tan, Mingyu Chen: Poster: revisiting virtual channel memory for performance and fairness on multi-core architecture. ICS 2011: 379 |
| c51 | | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt: Prefetch-aware shared resource management for multi-core systems. ISCA 2011: 141-152 |
| c50 | | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu: Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees. ISCA 2011: 401-412 |
| c49 | | Onur Mutlu: Memory systems in the many-core era: challenges, opportunities, and solution directions. ISMM 2011: 77-78 |
| c48 | | Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt: Improving GPU performance via large warps and two-level warp scheduling. MICRO 2011: 308-317 |
| c47 | | Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt: Parallel application memory scheduling. MICRO 2011: 362-373 |
| c46 | | Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda: Reducing memory interference in multicore systems via application-aware memory channel partitioning. MICRO 2011: 374-385 |
| c45 | | Michael Papamichael, James C. Hoe, Onur Mutlu: FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. NOCS 2011: 137-144 |
| 2010 | ||
| j17 | | Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger: Phase change memory architecture and the quest for scalability. Commun. ACM 53(7): 99-106 (2010) |
| j16 | | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt: Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro 30(1): 60-70 (2010) |
| j15 | | Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger: Phase-Change Technology and the Future of Main Memory. IEEE Micro 30(1): 143 (2010) |
| c44 | | Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Onur Mutlu, Mateo Valero: Efficient runahead threads. PACT 2010: 443-452 |
| c43 | | Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt: Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. ASPLOS 2010: 335-346 |
| c42 | | George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu: Next generation on-chip networks: what kind of congestion control do we need? HotNets 2010: 12 |
| c41 | | Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter: ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. HPCA 2010: 1-12 |
| c40 | | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Aérgia: exploiting packet latency slack in on-chip networks. ISCA 2010: 106-116 |
| c39 | | Boris Grot, Stephen W. Keckler, Onur Mutlu: Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors. ISCA Workshops 2010: 357-375 |
| c38 | | M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt: Data marshaling for multi-core architectures. ISCA 2010: 441-450 |
| c37 | | Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter: Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. MICRO 2010: 65-76 |
| c36 | | Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu: QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors. NOCS 2010: 241-248 |
| c35 | | Yanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra: Concurrent autonomous self-test for uncore components in system-on-chips. VTS 2010: 232-237 |
| 2009 | ||
| j14 | | Onur Mutlu, Thomas Moscibroda: Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers. IEEE Micro 29(1): 22-32 (2009) |
| j13 | | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: A Flexible Software-Based Framework for Online Detection of Hardware Defects. IEEE Trans. Computers 58(8): 1063-1079 (2009) |
| j12 | | Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. IEEE Trans. Computers 58(9): 1153-1170 (2009) |
| c34 | | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt: Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS 2009: 253-264 |
| c33 | | Eiman Ebrahimi, Onur Mutlu, Yale N. Patt: Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. HPCA 2009: 7-17 |
| c32 | | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu: Express Cube Topologies for on-Chip Interconnects. HPCA 2009: 163-174 |
| c31 | | Yanjing Li, Onur Mutlu, Subhasish Mitra: Operating system scheduling for efficient online self-test in robust systems. ICCAD 2009: 201-208 |
| c30 | | Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger: Architecting phase change memory as a scalable dram alternative. ISCA 2009: 2-13 |
| c29 | | Thomas Moscibroda, Onur Mutlu: A case for bufferless routing in on-chip networks. ISCA 2009: 196-207 |
| c28 | | José A. Joao, Onur Mutlu, Yale N. Patt: Flexible reference-counting-based hardware acceleration for garbage collection. ISCA 2009: 418-428 |
| c27 | | Boris Grot, Stephen W. Keckler, Onur Mutlu: Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip. MICRO 2009: 268-279 |
| c26 | | Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das: Application-aware prioritization mechanisms for on-chip networks. MICRO 2009: 280-291 |
| c25 | | Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt: Coordinated control of multiple prefetchers in multi-core systems. MICRO 2009: 316-326 |
| c24 | | Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt: Improving memory bank-level parallelism in the presence of prefetching. MICRO 2009: 327-336 |
| 2008 | ||
| j11 | | Sangyeun Cho, Tao Li, Onur Mutlu: Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems. IEEE Micro 28(3): 2-5 (2008) |
| c23 | | José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt: Improving the performance of object-oriented languages with dynamic predication of indirect jumps. ASPLOS 2008: 80-90 |
| c22 | | Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Performance-aware speculation control using wrong path usefulness prediction. HPCA 2008: 39-49 |
| c21 | | Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana: Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. ISCA 2008: 39-50 |
| c20 | | Onur Mutlu, Thomas Moscibroda: Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. ISCA 2008: 63-74 |
| c19 | | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt: Prefetch-Aware DRAM Controllers. MICRO 2008: 200-209 |
| c18 | | Kypros Constantinides, Onur Mutlu, Todd M. Austin: Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. MICRO 2008: 282-293 |
| c17 | | Thomas Moscibroda, Onur Mutlu: Distributed order scheduling and its application to multi-core dram controllers. PODC 2008: 365-374 |
| e1 |  | David Christie, Alan Lee, Onur Mutlu, Benjamin G. Zorn (Eds.): 4th International Symposium on Workload Characterization (IISWC 2008), Seattle, Washington, USA, September 14-16, 2008. IEEE 2008, isbn 978-1-4244-2778-9 |
| 2007 | ||
| j10 | | José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Dynamic Predication of Indirect Jumps. Computer Architecture Letters 6(2): 25-28 (2007) |
| j9 | | José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Dynamic Predication of Indirect Jumps. Computer Architecture Letters 7(1): 1-4 (2007) |
| j8 | | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. IEEE Micro 27(1): 94-104 (2007) |
| c16 | | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. CGO 2007: 367-378 |
| c15 | | Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt: Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. HPCA 2007: 63-74 |
| c14 | | Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA 2007: 424-435 |
| c13 | | Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco: Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. MICRO 2007: 97-108 |
| c12 | | Onur Mutlu, Thomas Moscibroda: Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. MICRO 2007: 146-160 |
| 2006 | ||
| j7 | | Onur Mutlu, Hyesoon Kim, Yale N. Patt: Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. IEEE Micro 26(1): 10-20 (2006) |
| j6 | | Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark: Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. IEEE Micro 26(1): 48-58 (2006) |
| j5 | | Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. IEEE Trans. Computers 55(12): 1491-1508 (2006) |
| c11 | | Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt: 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. CGO 2006: 159-172 |
| c10 | | Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt: A Case for MLP-Aware Cache Replacement. ISCA 2006: 167-178 |
| c9 | | Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt: Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. MICRO 2006: 53-64 |
| 2005 | ||
| j4 | | Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt: On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. Computer Architecture Letters 4(1): 2 (2005) |
| j3 | | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. International Journal of Parallel Programming 33(5): 529-559 (2005) |
| j2 | | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. IEEE Trans. Computers 54(12): 1556-1571 (2005) |
| c8 | | Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt: Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN 2005: 434-443 |
| c7 | | Onur Mutlu, Hyesoon Kim, Yale N. Patt: Techniques for Efficient Processing in Runahead Execution Engines. ISCA 2005: 370-381 |
| c6 | | Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt: Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. MICRO 2005: 43-54 |
| c5 | | Onur Mutlu, Hyesoon Kim, Yale N. Patt: Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO 2005: 233-244 |
| 2004 | ||
| c4 | | David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt: Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. MICRO 2004: 119-128 |
| c3 | | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. SBAC-PAD 2004: 2-9 |
| c2 | | Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt: Understanding the effects of wrong-path memory references on processor performance. WMPI 2004: 56-64 |
| 2003 | ||
| j1 | | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt: Runahead Execution: An Effective Alternative to Large Instruction Windows. IEEE Micro 23(6): 20-25 (2003) |
| c1 | | Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. HPCA 2003: 129-140 |
Colors in the list of coauthors
Last update Fri May 24 04:06:13 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page