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Madhu Mutyam
Author information
- affiliation: Department of Computer Science and Engineering, Indian Institute of Technology, Madras, India
2010 – today
- 2013
[c25]Tripti Warrier, B. Anupama, Madhu Mutyam: An Application-Aware Cache Replacement Policy for Last-Level Caches. ARCS 2013: 207-219- [c24]John Jose, Bhawna Nayak, Kranthi Kumar, Madhu Mutyam: DeBAR: deflection based adaptive router with minimal buffering. DATE 2013: 1583-1588
- 2012
- [j19]Madhu Mutyam: Fibonacci Codes for Crosstalk Avoidance. IEEE Trans. VLSI Syst. 20(10): 1899-1903 (2012)
- [c23]Raghavendra K, Tripti Warrier, Madhu Mutyam: SkipCache: miss-rate aware cache management. PACT 2012: 481-482
- [c22]John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam: TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. ICCAD 2012: 564-568
- [c21]C. J. Janraj, T. Venkata Kalyan, Tripti Warrier, Madhu Mutyam: Way Sharing Set Associative Cache Architecture. VLSI Design 2012: 251-256
- 2011
- [j18]Kartikey Mittal, Arpit Joshi, Madhu Mutyam: Timing variation-aware scheduling and resource binding in high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 16(4): 40 (2011)
- [c20]Arpit Joshi, Madhu Mutyam: Prevention flow-control for low latency torus networks-on-chip. NOCS 2011: 41-48
2000 – 2009
- 2009
- [j17]Nallamothu Satyanarayana, A. Vinaya Babu, Madhu Mutyam: Delay-efficient bus encoding techniques. Microprocessors and Microsystems - Embedded Hardware Design 33(5-6): 365-373 (2009)
- [j16]Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009)
- [j15]Madhu Mutyam: Selective shielding technique to eliminate crosstalk transitions. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)
- 2008
- [c19]Mohammed Abid Hussain, Madhu Mutyam: Block remap with turnoff: A variation-tolerant cache design technique. ASP-DAC 2008: 783-788
- [c18]
- [c17]Abu Saad Papa, Madhu Mutyam: Power management of variation aware chip multiprocessors. ACM Great Lakes Symposium on VLSI 2008: 423-428
- [c16]T. Venkata Kalyan, Madhu Mutyam: Word-interleaved cache: an energy efficient data cache architecture. ISLPED 2008: 265-270
- [c15]T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao: Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. VLSI Design 2008: 235-241
- 2007
- [c14]Madhu Mutyam, Narayanan Vijaykrishnan: Working with process variation aware caches. DATE 2007: 1152-1157
- [c13]
- [c12]Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338
- [c11]Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin: Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI 2007: 375-382
- [c10]Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu: Exploiting on-chip data behavior for delay minimization. SLIP 2007: 103-110
- 2006
- [j14]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam: Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. J. Low Power Electronics 2(3): 425-436 (2006)
- [c9]K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam: Delay and peak power minimization for on-chip buses using temporal redundancy. ACM Great Lakes Symposium on VLSI 2006: 119-122
- [c8]Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360
- [c7]Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Compiler-directed thermal management for VLIW functional units. LCTES 2006: 163-172
- 2005
- [j13]Madhu Mutyam, Kamala Krithivasan, A. Siddhartha Reddy: On Characterizing Recursively Enumerable Languages by Insertion Grammars. Fundam. Inform. 64(1-4): 317-324 (2005)
- [j12]Madhu Mutyam: Rewriting P systems: improved hierarchies. Theor. Comput. Sci. 334(1-3): 161-175 (2005)
- 2004
- [j11]Madhu Mutyam: Descriptional Complexity of Rewriting P Systems. Journal of Automata, Languages and Combinatorics 9(2/3): 311-316 (2004)
- [j10]Madhu Mutyam, Kamala Krithivasan: Length Synchronization Context-Free Grammars. Journal of Automata, Languages and Combinatorics 9(4): 457-464 (2004)
- [j9]Madhu Mutyam, Vaka Jaya Prakash, Kamala Krithivasan: Rewriting Tissue P Systems. J. UCS 10(9): 1250-1271 (2004)
- [c6]P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam: A Bus Encoding Technique for Power and Cross-talk Minimization. VLSI Design 2004: 443-448
- [c5]
- 2003
- [j8]Madhu Mutyam, Kamala Krithivasan: On a class of P automata. Int. J. Comput. Math. 80(9): 1111-1120 (2003)
- [j7]
- [j6]M. Sakthi Balan, Kamala Krithivasan, Madhu Mutyam: Some Variants in Communication of Parallel Communicating Pushdown Automata. Journal of Automata, Languages and Combinatorics 8(3): 401-416 (2003)
- [j5]Rodica Ceterchi, Madhu Mutyam, Gheorghe Paun, K. G. Subramanian: Array-rewriting P systems. Natural Computing 2(3): 229-249 (2003)
- 2002
- [j4]Madhu Mutyam, Kamala Krithivasan: Generalized normal form for rewriting P systems. Acta Inf. 38(10): 721-734 (2002)
- [j3]Madhu Mutyam, Kamala Krithivasan: Improved Results about Universality of P systems. Bulletin of the EATCS 76: 162-168 (2002)
- [j2]
- [j1]
- [c4]
- [c3]
- 2001
- [c2]Madhu Mutyam, Kamala Krithivasan: P Systems with Membrane Creation: Universality and Efficiency. MCU 2001: 276-287
- 2000
- [c1]Madhu Mutyam, Kamala Krithivasan: Universality Results for Some Variants of P Systems. WMP 2000: 237-254
Coauthor Index
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last updated on 2013-05-19 19:34 CEST by the dblp team